caravel/verilog
Tim Edwards 5d3f2a26f4 Corrected the Caravel layout and the Caravel and Caravan GL netlists
to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side.  Caravel is now LVS clean again (Caravan needs layout
work).
2021-11-23 11:47:17 -05:00
..
dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl Corrected the Caravel layout and the Caravel and Caravan GL netlists 2021-11-23 11:47:17 -05:00
rtl Made updates to correct LVS errors in caravan. Found one major error in the RTL 2021-11-22 22:35:52 -05:00