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caravel/verilog/gl/gpio_control_block.v

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harden gpio_control_block
2021-11-04 09:19:12 -05:00
module gpio_control_block (mgmt_gpio_in,
mgmt_gpio_oeb,
mgmt_gpio_out,
one,
pad_gpio_ana_en,
pad_gpio_ana_pol,
pad_gpio_ana_sel,
pad_gpio_holdover,
pad_gpio_ib_mode_sel,
pad_gpio_in,
pad_gpio_inenb,
pad_gpio_out,
pad_gpio_outenb,
pad_gpio_slow_sel,
pad_gpio_vtrip_sel,
resetn,
resetn_out,
serial_clock,
serial_clock_out,
serial_data_in,
serial_data_out,
serial_load,
serial_load_out,
user_gpio_in,
user_gpio_oeb,
user_gpio_out,
vccd,
vccd1,
vssd,
vssd1,
zero,
gpio_defaults,
pad_gpio_dm);
output mgmt_gpio_in;
input mgmt_gpio_oeb;
input mgmt_gpio_out;
output one;
output pad_gpio_ana_en;
output pad_gpio_ana_pol;
output pad_gpio_ana_sel;
output pad_gpio_holdover;
output pad_gpio_ib_mode_sel;
input pad_gpio_in;
output pad_gpio_inenb;
output pad_gpio_out;
output pad_gpio_outenb;
output pad_gpio_slow_sel;
output pad_gpio_vtrip_sel;
input resetn;
output resetn_out;
input serial_clock;
output serial_clock_out;
input serial_data_in;
output serial_data_out;
input serial_load;
output serial_load_out;
output user_gpio_in;
input user_gpio_oeb;
input user_gpio_out;
input vccd;
input vccd1;
input vssd;
input vssd1;
output zero;
input [12:0] gpio_defaults;
output [2:0] pad_gpio_dm;
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire _058_;
wire _059_;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire clknet_0_serial_clock;
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
wire clknet_0_serial_load;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
wire clknet_1_0__leaf_serial_clock;
wire clknet_1_0__leaf_serial_load;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire gpio_logic1;
wire gpio_outenb;
wire mgmt_ena;
wire net1;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net2;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire net28;
wire net29;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire net3;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire net4;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire net5;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire net6;
wire net7;
wire net8;
wire net9;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire one_buffered;
wire serial_clock_out_buffered;
wire serial_load_out_buffered;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire \shift_register[0] ;
wire \shift_register[10] ;
wire \shift_register[11] ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
wire \shift_register[12] ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
wire \shift_register[1] ;
wire \shift_register[2] ;
wire \shift_register[3] ;
wire \shift_register[4] ;
wire \shift_register[5] ;
wire \shift_register[6] ;
wire \shift_register[7] ;
wire \shift_register[8] ;
wire \shift_register[9] ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
wire zero_buffered;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__065__A0 (.DIODE(user_gpio_oeb),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__066__B (.DIODE(user_gpio_out),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__071__B (.DIODE(gpio_defaults[0]),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__072__B (.DIODE(gpio_defaults[0]),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__073__A (.DIODE(net23),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__073__B (.DIODE(gpio_defaults[2]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__074__A_N (.DIODE(net23),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__074__B (.DIODE(gpio_defaults[2]),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__075__B (.DIODE(gpio_defaults[8]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__076__B (.DIODE(gpio_defaults[8]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__077__B (.DIODE(gpio_defaults[9]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__078__B (.DIODE(gpio_defaults[9]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__079__A (.DIODE(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__079__B (.DIODE(gpio_defaults[3]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__080__A_N (.DIODE(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__080__B (.DIODE(gpio_defaults[3]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__081__B (.DIODE(gpio_defaults[4]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__082__B (.DIODE(gpio_defaults[4]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__083__A (.DIODE(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__083__B (.DIODE(gpio_defaults[1]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__084__A_N (.DIODE(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__084__B (.DIODE(gpio_defaults[1]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__085__B (.DIODE(gpio_defaults[10]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__086__B (.DIODE(gpio_defaults[10]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__087__B (.DIODE(gpio_defaults[11]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__088__B (.DIODE(gpio_defaults[11]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__089__B (.DIODE(gpio_defaults[12]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__090__B (.DIODE(gpio_defaults[12]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__091__B (.DIODE(gpio_defaults[5]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__092__B (.DIODE(gpio_defaults[5]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__093__B (.DIODE(gpio_defaults[6]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__094__B (.DIODE(gpio_defaults[6]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__095__B (.DIODE(gpio_defaults[7]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__096__B (.DIODE(gpio_defaults[7]),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA__125__RESET_B (.DIODE(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_clock_A (.DIODE(serial_clock),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_load_A (.DIODE(serial_load),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(mgmt_gpio_oeb),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(mgmt_gpio_out),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(pad_gpio_in),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(resetn),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(serial_data_in),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_0_3 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_0_31 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_0_57 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_0_91 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_10_85 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_14_98 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_17_98 (.VGND(vssd),
Update gpio_control block
2021-11-04 10:58:58 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_19_55 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_19_70 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__decap_3 FILLER_1_32 (.VGND(vssd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_1_98 (.VGND(vssd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_20_98 (.VGND(vssd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__decap_6 FILLER_2_42 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_2_48 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_2_52 (.VGND(vssd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_3_48 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_3_80 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_5_56 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_5_98 (.VGND(vssd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_7_98 (.VGND(vssd),
gpio_control_block constrains fix (#69) Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 13:50:54 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_8_52 (.VGND(vssd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__fill_1 FILLER_8_98 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
Update gpio_control_block
2021-11-05 09:54:24 -05:00
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
harden gpio_control_block
2021-11-04 09:19:12 -05:00
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
harden gpio_control_block
2021-11-04 09:19:12 -05:00
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(vssd),
.VPWR(vccd));
Update gpio_control_block
2021-11-05 09:54:24 -05:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(vssd),
.VPWR(vccd));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(vssd),
.VPWR(vccd));
sky130_fd_sc_hd__inv_2 _060_ (.A(net3),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_001_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__inv_2 _061__1 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net29));
sky130_fd_sc_hd__inv_2 _062__14 (.A(clknet_1_0__leaf_serial_clock),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net42));
sky130_fd_sc_hd__nand2b_2 _063_ (.A_N(net14),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_outenb),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(_047_));
sky130_fd_sc_hd__and2_0 _064_ (.A(gpio_outenb),
.B(net1),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_042_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__mux2_4 _065_ (.A0(user_gpio_oeb),
.A1(_042_),
.S(mgmt_ena),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net16));
sky130_fd_sc_hd__nand2b_2 _066_ (.A_N(mgmt_ena),
.B(user_gpio_out),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(_043_));
sky130_fd_sc_hd__and3b_2 _067_ (.A_N(net11),
.B(net10),
.C(net1),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_044_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__and2b_2 _068_ (.A_N(_000_),
.B(_044_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(_045_));
sky130_fd_sc_hd__o21ai_2 _069_ (.A1(net2),
.A2(_044_),
.B1(mgmt_ena),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.Y(_046_));
sky130_fd_sc_hd__o21ai_4 _070_ (.A1(_045_),
.A2(_046_),
.B1(_043_),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.Y(net15));
sky130_fd_sc_hd__or2_0 _071_ (.A(net25),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[0]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_002_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _072_ (.A_N(net24),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[0]),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_003_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _073_ (.A(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[2]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_004_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _074_ (.A_N(net23),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[2]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_005_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _075_ (.A(net27),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[8]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_006_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _076_ (.A_N(net27),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[8]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_007_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _077_ (.A(net25),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[9]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_008_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _078_ (.A_N(net27),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[9]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_009_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _079_ (.A(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[3]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_010_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _080_ (.A_N(net23),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[3]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_011_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _081_ (.A(net21),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[4]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_012_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _082_ (.A_N(net21),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[4]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_013_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _083_ (.A(net23),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[1]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_014_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _084_ (.A_N(net23),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[1]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_015_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _085_ (.A(net27),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[10]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_016_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _086_ (.A_N(net27),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[10]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_017_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _087_ (.A(net25),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[11]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(_018_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _088_ (.A_N(net25),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[11]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_019_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _089_ (.A(net25),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.B(gpio_defaults[12]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_020_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _090_ (.A_N(net26),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[12]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_021_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _091_ (.A(net21),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[5]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_022_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _092_ (.A_N(net21),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[5]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_023_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _093_ (.A(net22),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[6]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_024_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _094_ (.A_N(net21),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[6]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_025_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__or2_0 _095_ (.A(net22),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[7]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(_026_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__nand2b_2 _096_ (.A_N(net22),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.B(gpio_defaults[7]),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Y(_027_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__inv_2 _097__2 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net30));
sky130_fd_sc_hd__inv_2 _098__3 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net31));
sky130_fd_sc_hd__inv_2 _099__4 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net32));
sky130_fd_sc_hd__inv_2 _100__5 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net33));
sky130_fd_sc_hd__inv_2 _101__6 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net34));
sky130_fd_sc_hd__inv_2 _102__7 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net35));
sky130_fd_sc_hd__inv_2 _103__8 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net36));
sky130_fd_sc_hd__inv_2 _104__9 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net37));
sky130_fd_sc_hd__inv_2 _105__10 (.A(serial_load_out_buffered),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net38));
sky130_fd_sc_hd__inv_2 _106__11 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net39));
sky130_fd_sc_hd__inv_2 _107__12 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net40));
sky130_fd_sc_hd__inv_2 _108__13 (.A(clknet_1_0__leaf_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Y(net41));
sky130_fd_sc_hd__dfbbn_2 _109_ (.CLK_N(net29),
.D(net45),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_002_),
.SET_B(_003_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.Q(mgmt_ena),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q_N(_058_));
sky130_fd_sc_hd__dfbbn_2 _110_ (.CLK_N(net30),
.D(net46),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_004_),
.SET_B(_005_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net12),
.Q_N(_057_));
sky130_fd_sc_hd__dfbbn_2 _111_ (.CLK_N(net31),
.D(net54),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.RESET_B(_006_),
.SET_B(_007_),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net17),
.Q_N(_056_));
sky130_fd_sc_hd__dfbbn_2 _112_ (.CLK_N(net32),
.D(net43),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_008_),
.SET_B(_009_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net18),
.Q_N(_055_));
sky130_fd_sc_hd__dfbbn_2 _113_ (.CLK_N(net33),
.D(net48),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_010_),
.SET_B(_011_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net14),
.Q_N(_054_));
sky130_fd_sc_hd__dfbbn_2 _114_ (.CLK_N(net34),
.D(net55),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_012_),
.SET_B(_013_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net13),
.Q_N(_053_));
sky130_fd_sc_hd__dfbbn_2 _115_ (.CLK_N(net35),
.D(net47),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_014_),
.SET_B(_015_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(gpio_outenb),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q_N(_052_));
sky130_fd_sc_hd__dfbbn_2 _116_ (.CLK_N(net36),
.D(net52),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_016_),
.SET_B(_017_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net9),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.Q_N(_000_));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfbbn_2 _117_ (.CLK_N(net37),
.D(net44),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_018_),
.SET_B(_019_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net10),
.Q_N(_051_));
sky130_fd_sc_hd__dfbbn_2 _118_ (.CLK_N(net38),
.D(net49),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_020_),
.SET_B(_021_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net11),
.Q_N(_050_));
sky130_fd_sc_hd__dfbbn_2 _119_ (.CLK_N(net39),
.D(net53),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_022_),
.SET_B(_023_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net6),
.Q_N(_049_));
sky130_fd_sc_hd__dfbbn_2 _120_ (.CLK_N(net40),
.D(net51),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_024_),
.SET_B(_025_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net8),
.Q_N(_048_));
sky130_fd_sc_hd__dfbbn_2 _121_ (.CLK_N(net41),
.D(net50),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.RESET_B(_026_),
.SET_B(_027_),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net7),
.Q_N(_059_));
sky130_fd_sc_hd__dfrtp_4 _122_ (.CLK(serial_clock_out_buffered),
.D(net5),
.RESET_B(net24),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[0] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _123_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net45),
.RESET_B(net24),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[1] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _124_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net47),
.RESET_B(net24),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[2] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _125_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net46),
.RESET_B(net23),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[3] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _126_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net48),
.RESET_B(net21),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[4] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _127_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net55),
.RESET_B(net21),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[5] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _128_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net53),
.RESET_B(net22),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[6] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _129_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net51),
.RESET_B(net22),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[7] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _130_ (.CLK(clknet_1_0__leaf_serial_clock),
.D(net50),
.RESET_B(net22),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[8] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _131_ (.CLK(serial_clock_out_buffered),
.D(net54),
.RESET_B(net27),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[9] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _132_ (.CLK(serial_clock_out_buffered),
.D(net43),
.RESET_B(net27),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[10] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _133_ (.CLK(serial_clock_out_buffered),
.D(net52),
.RESET_B(net25),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
.Q(\shift_register[11] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_4 _134_ (.CLK(serial_clock_out_buffered),
.D(net44),
.RESET_B(net25),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Q(\shift_register[12] ));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dfrtp_2 _135_ (.CLK(net42),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.D(\shift_register[12] ),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.RESET_B(net26),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.Q(net20));
sky130_fd_sc_hd__buf_2 _136_ (.A(net26),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net19));
sky130_fd_sc_hd__ebufn_8 _139_ (.A(net3),
.TE_B(_047_),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.Z(mgmt_gpio_in));
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_clock (.A(serial_clock),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(clknet_0_serial_clock));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_load (.A(serial_load),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.X(clknet_0_serial_load));
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_serial_clock (.A(clknet_0_serial_clock),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(clknet_1_0__leaf_serial_clock));
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_serial_load (.A(clknet_0_serial_load),
Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency
2021-11-05 11:36:43 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
.X(clknet_1_0__leaf_serial_load));
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_1__f_serial_clock (.A(clknet_0_serial_clock),
Update gpio_control_block
2021-11-05 09:54:24 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(serial_clock_out_buffered));
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_1__f_serial_load (.A(clknet_0_serial_load),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(serial_load_out_buffered));
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
sky130_fd_sc_hd__conb_1 const_source (.VGND(vssd),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.HI(one_buffered),
.LO(zero_buffered));
sky130_fd_sc_hd__buf_2 fanout21 (.A(net22),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net21));
sky130_fd_sc_hd__buf_2 fanout22 (.A(net28),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net22));
sky130_fd_sc_hd__buf_2 fanout23 (.A(net24),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net23));
sky130_fd_sc_hd__buf_2 fanout24 (.A(net28),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net24));
sky130_fd_sc_hd__buf_2 fanout25 (.A(net28),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net25));
sky130_fd_sc_hd__buf_2 fanout26 (.A(net28),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net26));
sky130_fd_sc_hd__buf_2 fanout27 (.A(net28),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net27));
sky130_fd_sc_hd__buf_2 fanout28 (.A(net4),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net28));
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
sky130_fd_sc_hd__einvp_8 gpio_in_buf (.A(_001_),
.TE(gpio_logic1),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
.Z(user_gpio_in));
gpio_logic_high gpio_logic_high (.gpio_logic1(gpio_logic1),
.vccd1(vccd1),
.vssd1(vssd1));
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(\shift_register[9] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net43));
sky130_fd_sc_hd__dlygate4sd3_1 hold10 (.A(\shift_register[10] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net52));
sky130_fd_sc_hd__dlygate4sd3_1 hold11 (.A(\shift_register[5] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net53));
sky130_fd_sc_hd__dlygate4sd3_1 hold12 (.A(\shift_register[8] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net54));
sky130_fd_sc_hd__dlygate4sd3_1 hold13 (.A(\shift_register[4] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net55));
sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(\shift_register[11] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net44));
sky130_fd_sc_hd__dlygate4sd3_1 hold3 (.A(\shift_register[0] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net45));
sky130_fd_sc_hd__dlygate4sd3_1 hold4 (.A(\shift_register[2] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net46));
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(\shift_register[1] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net47));
sky130_fd_sc_hd__dlygate4sd3_1 hold6 (.A(\shift_register[3] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net48));
sky130_fd_sc_hd__dlygate4sd3_1 hold7 (.A(\shift_register[12] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net49));
sky130_fd_sc_hd__dlygate4sd3_1 hold8 (.A(\shift_register[7] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net50));
sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(\shift_register[6] ),
harden gpio_control_block
2021-11-04 09:19:12 -05:00
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
.VPWR(vccd),
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
.X(net51));
sky130_fd_sc_hd__buf_2 input1 (.A(mgmt_gpio_oeb),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net1));
sky130_fd_sc_hd__buf_2 input2 (.A(mgmt_gpio_out),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net2));
sky130_fd_sc_hd__buf_2 input3 (.A(pad_gpio_in),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net3));
sky130_fd_sc_hd__buf_2 input4 (.A(resetn),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net4));
sky130_fd_sc_hd__buf_2 input5 (.A(serial_data_in),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(net5));
sky130_fd_sc_hd__buf_16 one_buffer (.A(one_buffered),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(one));
sky130_fd_sc_hd__buf_16 output10 (.A(net10),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_dm[1]));
sky130_fd_sc_hd__buf_16 output11 (.A(net11),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_dm[2]));
sky130_fd_sc_hd__buf_16 output12 (.A(net12),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_holdover));
sky130_fd_sc_hd__buf_16 output13 (.A(net13),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_ib_mode_sel));
sky130_fd_sc_hd__buf_16 output14 (.A(net14),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_inenb));
sky130_fd_sc_hd__buf_16 output15 (.A(net15),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_out));
sky130_fd_sc_hd__buf_16 output16 (.A(net16),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_outenb));
sky130_fd_sc_hd__buf_16 output17 (.A(net17),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_slow_sel));
sky130_fd_sc_hd__buf_16 output18 (.A(net18),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_vtrip_sel));
sky130_fd_sc_hd__buf_16 output19 (.A(net19),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(resetn_out));
sky130_fd_sc_hd__buf_16 output20 (.A(net20),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(serial_data_out));
sky130_fd_sc_hd__buf_16 output6 (.A(net6),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_ana_en));
sky130_fd_sc_hd__buf_16 output7 (.A(net7),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_ana_pol));
sky130_fd_sc_hd__buf_16 output8 (.A(net8),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_ana_sel));
sky130_fd_sc_hd__buf_16 output9 (.A(net9),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_dm[0]));
sky130_fd_sc_hd__clkbuf_16 serial_clock_out_buffer (.A(serial_clock_out_buffered),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(serial_clock_out));
sky130_fd_sc_hd__clkbuf_16 serial_load_out_buffer (.A(serial_load_out_buffered),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(serial_load_out));
sky130_fd_sc_hd__buf_16 zero_buffer (.A(zero_buffered),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd),
.X(zero));
harden gpio_control_block
2021-11-04 09:19:12 -05:00
endmodule