32 Commits

Author	SHA1	Message	Date
tangxifan	6814b3bb60	[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants	2020-12-02 15:22:19 -07:00
tangxifan	20cba3f558	[Testbench] Add testbench for post-PnR verification for FPGA with reset	2020-12-02 13:43:06 -07:00
tangxifan	61163de580	[Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset	2020-12-02 12:00:28 -07:00
tangxifan	c676db1fe4	[Testbench] Bug fix in the ccff post-pnr testbench template	2020-11-30 11:18:42 -07:00
tangxifan	c638edfc14	[Testbench] Regenerate ccff/scff testbenches for wrapper	2020-11-30 10:33:50 -07:00
tangxifan	e63cb7ca89	[Testbench] Rename testbench top module to be compatible with verification scripts	2020-11-30 10:23:30 -07:00
tangxifan	c70d5ac4f0	[Testbench] Add ccff test wrapper testbench and include netlist	2020-11-30 09:42:31 -07:00
tangxifan	2b40d5fb4b	[HDL] Bug fix	2020-11-30 09:34:26 -07:00
tangxifan	fc3eadaf29	[Testbench] Add SCFF test for wrapper	2020-11-29 22:58:48 -07:00
tangxifan	0bf5a400e8	[Testbench] Add include netlists for wrapper testbenches	2020-11-29 22:48:25 -07:00
tangxifan	e3efcebf2b	[Testbench] Bug fix in include netlist	2020-11-29 21:00:20 -07:00
tangxifan	4ab69d925c	[Testbench] Add include netlist for wrapper testbench	2020-11-29 20:46:50 -07:00
tangxifan	969ef7976f	[Testbench] Remove those with problems in convergence	2020-11-28 15:24:54 -07:00
tangxifan	3c685311e9	[Testbench] Bug fix for the ccff testbench to sync with latest netlist	2020-11-28 15:22:50 -07:00
tangxifan	2380783808	[Testbench] Remove post pnr testbenches that can be auto-generated	2020-11-28 14:46:27 -07:00
tangxifan	b2ebac3b23	[Testbench] Rename post-PnR testbenches to ease modelsim batch jobs	2020-11-28 11:14:34 -07:00
tangxifan	0c9953a26e	[Testbench] Update post-PnR testbenches to synchornize with latest netlist	2020-11-28 11:09:55 -07:00
tangxifan	42e188732d	[Testbench] Use python to auto-generate the post-pnr testbenches	2020-11-27 14:17:56 -07:00
tangxifan	98917a51bc	[Testbench] Update post pnr testbench with signal initialization	2020-11-23 16:24:50 -07:00
tangxifan	1c40ab68a1	[Testbench] Add post PnR testbench for and2_or2 benchmark	2020-11-22 13:45:16 -07:00
tangxifan	06c732325b	[Testbench] Add post-PnR testbench for benchmark simon_serial	2020-11-20 17:05:42 -07:00
tangxifan	5edb154140	[Testbench] Add post PnR testbench for benchmark bin2bcd	2020-11-20 16:59:38 -07:00
tangxifan	b60e0aa2cd	[Testbench] Add post-PnR testbench for benchmark routing_test	2020-11-20 16:47:03 -07:00
tangxifan	aa79cc3577	[Testbench] Add post-PnR testbench for benchmark counter	2020-11-20 16:34:32 -07:00
tangxifan	5a2f1e7607	[TESTBENCH] Place the include lines for post-PnR skywater cell netlists in a separated netlist, so that it can be shared among post-PnRed testbenches	2020-11-20 13:33:13 -07:00
tangxifan	40eccfa0ba	[Testbench] Update post-PnR testbenches for configuration chain and scan-chain and enhance checking codes	2020-11-20 11:45:51 -07:00
tangxifan	ae82946052	[Testbench] Update and2_latch post-pnr testbench	2020-11-20 11:15:01 -07:00
tangxifan	e58fc97794	[Testbench] Update post-pnr test for latest PnRed netlist	2020-11-20 10:55:59 -07:00
tangxifan	f5d18d33ea	[Testbench] Add scan-chain testbench for post-pnr verification	2020-11-18 16:23:37 -07:00
tangxifan	439c73d211	[Testbench] Add configuration chain test benches for pre- and post- pnr simulation	2020-11-18 15:58:00 -07:00
tangxifan	0681e34a1b	[Testbench] Add post PnR testbench for and2_latch benchmark	2020-11-17 17:39:53 -07:00
tangxifan	804d96bf50	[Testbench] Rename post-pnr testbenches to dedicated directories	2020-11-17 13:45:55 -07:00