[Testbench] Update post pnr testbench with signal initialization

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tangxifan 2020-11-23 16:24:50 -07:00

parent 73de63d41c

commit 98917a51bc

1 changed files with 1375672 additions and 1 deletions

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TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v

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