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600 Commits 16 Branches 1 Tag 1.8 GiB
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600 Commits

Author SHA1 Message Date
tangxifan 3a6b0c18f7 [CI] Bug fix 2020-11-30 20:35:56 -07:00
tangxifan ef2d19aafa [CI] Bug fix 2020-11-30 20:27:41 -07:00
tangxifan e0d9eb9e7f [CI] Add debugging info 2020-11-30 20:18:19 -07:00
tangxifan 582b3afa6d [CI] Use native cmake build commands 2020-11-30 20:14:43 -07:00
tangxifan 27b16b3619 [CI] Bug fix 2020-11-30 20:06:03 -07:00
tangxifan 58d4f1835c [CI] Try to correct path when checking out OpenFPGA 2020-11-30 20:01:56 -07:00
tangxifan e19201e9db [CI] Fix the wrong path to checkout OpenFPGA 2020-11-30 19:59:38 -07:00
tangxifan cf8b83e271 [CI] Try another format of repo address 2020-11-30 19:53:54 -07:00
tangxifan 7cb188fc5c [CI] Try to give a correct repo path 2020-11-30 19:52:14 -07:00
tangxifan e66b2648da [CI] Bug fix 2020-11-30 19:47:15 -07:00
tangxifan 54dbae1503 [CI] Try bug fix 2020-11-30 19:45:12 -07:00
tangxifan 6fe1609f91 [Test] Add CI test 2020-11-30 18:51:35 -07:00
tangxifan e7fae9a32d [Git] Remove submodules 2020-11-30 18:34:04 -07:00
tangxifan e71b5eb3f4 [Git] add OpenFPGA as a submodule 2020-11-30 18:25:11 -07:00
Laboratory for Nano Integrated Systems (LNIS) f4397e1656
Merge pull request #47 from LNIS-Projects/xt_dev 
Bug fix in the arch port naming
 2020-11-30 18:23:38 -07:00
tangxifan be9399a016 [Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA 2020-11-30 17:58:56 -07:00
tangxifan c1db942cc6
Merge pull request #46 from LNIS-Projects/tpagarani_dev 
modify carry chain to change output mux
 2020-11-30 13:57:56 -07:00
Laboratory for Nano Integrated Systems (LNIS) 0c5b378592
Merge pull request #45 from LNIS-Projects/xt_dev 
Wrapper Testbench Converter
 2020-11-30 11:44:00 -07:00
tangxifan c676db1fe4 [Testbench] Bug fix in the ccff post-pnr testbench template 2020-11-30 11:18:42 -07:00
tangxifan c638edfc14 [Testbench] Regenerate ccff/scff testbenches for wrapper 2020-11-30 10:33:50 -07:00
tangxifan a900cba5a5 [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
tangxifan e63cb7ca89 [Testbench] Rename testbench top module to be compatible with verification scripts 2020-11-30 10:23:30 -07:00
tangxifan c70d5ac4f0 [Testbench] Add ccff test wrapper testbench and include netlist 2020-11-30 09:42:31 -07:00
tangxifan 2b40d5fb4b [HDL] Bug fix 2020-11-30 09:34:26 -07:00
Tarachand Pagarani 9f7fb8a34d modify carry chain to change output mux 2020-11-30 07:08:09 -08:00
tangxifan fc3eadaf29 [Testbench] Add SCFF test for wrapper 2020-11-29 22:58:48 -07:00
tangxifan 0bf5a400e8 [Testbench] Add include netlists for wrapper testbenches 2020-11-29 22:48:25 -07:00
tangxifan 0ccc18d848 [Testbench] Bug fix in the paths to generate wrapper testbenches 2020-11-29 22:48:01 -07:00
tangxifan 931b93b83d [Testbench] Now wrapper testbench conversion can be batched 2020-11-29 22:38:16 -07:00
tangxifan 12c3e157bf [Testbench] Add a tempo fix on the analog pins 2020-11-29 22:32:36 -07:00
tangxifan 50089e11f9 [Testbench] Bug fix 2020-11-29 22:20:15 -07:00
tangxifan 4b681b88a6 [Testbench] Fix the unconnected wbs_we_i pin 2020-11-29 22:17:10 -07:00
tangxifan 724696a661 [Testbench] Add missing ports in the wrapper 2020-11-29 22:16:04 -07:00
tangxifan 5235424e83 [Testbench] Adapt path for signal init in testbench converter 2020-11-29 21:44:29 -07:00
tangxifan fec19ebc55 [Testbench] Typo fix 2020-11-29 21:19:56 -07:00
tangxifan 951f5f84ee [Testbench] Typo fix 2020-11-29 21:15:36 -07:00
tangxifan 78addbe294 [HDL] Name fix to be compatible with testbench generation 2020-11-29 21:01:44 -07:00
tangxifan e3efcebf2b [Testbench] Bug fix in include netlist 2020-11-29 21:00:20 -07:00
tangxifan 4ab69d925c [Testbench] Add include netlist for wrapper testbench 2020-11-29 20:46:50 -07:00
tangxifan eeb904a3e3 [Testbench] Typo fix in wrapper testbench converter 2020-11-29 20:32:59 -07:00
tangxifan a414a600a6 [Testbench] Bug fixed in wrapper testbench generator 2020-11-29 20:31:19 -07:00
tangxifan 64ae33066e [Testbench] Add script to convert post-PnR testbench for wrapper testbench 2020-11-29 20:23:34 -07:00
tangxifan fcee5f1c91 [HDL] Typo fix in pin assignment description 2020-11-29 18:02:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) b0b5b0b325
Merge pull request #44 from LNIS-Projects/xt_dev 
Upgraded Caravel Wrapper Generator
 2020-11-29 13:27:52 -07:00
tangxifan de5411db6b [HDL] Add pin assignement for v1.1 HD FPGA 2020-11-29 12:58:53 -07:00
tangxifan cdfa3d5ff4 [HDL] Update wrapper using the new generator 2020-11-29 12:47:52 -07:00
tangxifan d0f9ca718d [HDL] bug fix in wrapper line generator 2020-11-29 12:47:22 -07:00
tangxifan 9f82d9bf54 [HDL] Correct typo in wrapper generator 2020-11-29 12:39:56 -07:00
tangxifan 899018d503 [HDL] Bug fix in wrapper template 2020-11-29 12:38:25 -07:00
tangxifan ea758cd5b1 [HDL] Update wrapper template as most codes can be auto-generated 2020-11-29 12:36:23 -07:00