Ganesh Gore
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41f2844698
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[Action] And modify file and push action
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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62e0cffea1
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[Actions] Disables build test in ganesh_dev branch
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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d5a5ec5b1d
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[Actions] Testing repository fetch option
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2020-12-06 01:40:21 -07:00 |
Ganesh Gore
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452af85e98
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[Cleanup] Removed/Ignored testbench files from generated source
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
f5c1d9c0a0
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[Arch] enable local encoders
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
ad120e205b
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[CI] Add new arch to CI test
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
004f9dbcca
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[Arch] Bug fix in new arch
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
c015d65a03
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[Script] Add task run for custom cell FPGA architectures
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
4ddc6955a3
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[Arch] Add architecture using custom cells
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2020-12-06 01:40:21 -07:00 |
tangxifan
|
22451870dd
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[CI] Patch github repo path to sync with OpenFPGA repo movement
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2020-12-06 01:39:16 -07:00 |
tangxifan
|
87f79d78bb
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[CI] Add wrapper generator examples to CI
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2020-12-06 01:39:16 -07:00 |
tangxifan
|
696529b43d
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[Script] Increase routing chan width from 40 to 60 for version 1.2
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2020-12-06 01:39:16 -07:00 |
Ganesh Gore
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923a502c24
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[FPGA1212_v1.1] Added PostPnR files
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2020-12-02 01:43:58 -07:00 |
Ganesh Gore
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f385c0ca11
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[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist
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2020-12-02 01:43:05 -07:00 |
Ganesh Gore
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fd7a65c756
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-12-01 11:29:15 -07:00 |
Ganesh Gore
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a134cffb9d
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Added verilog files only in testbench directory in gitLFS
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2020-12-01 11:23:02 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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8713eb3c5b
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Merge pull request #48 from LNIS-Projects/xt_dev
Add Continuous Integration
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2020-12-01 08:56:35 -07:00 |
tangxifan
|
d867dbb1bf
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[Testbench] Bug fix in calling sub python script
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2020-12-01 08:14:43 -07:00 |
tangxifan
|
11d4b156b4
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[Testbench] Bug fix in finding scripts
|
2020-11-30 22:41:29 -07:00 |
tangxifan
|
6d5bb2d794
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[CI] Bug fix
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2020-11-30 22:38:24 -07:00 |
tangxifan
|
764e5310aa
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[Doc] Add badges to frontpage README
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2020-11-30 21:29:15 -07:00 |
tangxifan
|
2aa8f81421
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[CI] Add more tests
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2020-11-30 21:25:02 -07:00 |
tangxifan
|
3a6b0c18f7
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[CI] Bug fix
|
2020-11-30 20:35:56 -07:00 |
tangxifan
|
ef2d19aafa
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[CI] Bug fix
|
2020-11-30 20:27:41 -07:00 |
tangxifan
|
e0d9eb9e7f
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[CI] Add debugging info
|
2020-11-30 20:18:19 -07:00 |
tangxifan
|
582b3afa6d
|
[CI] Use native cmake build commands
|
2020-11-30 20:14:43 -07:00 |
tangxifan
|
27b16b3619
|
[CI] Bug fix
|
2020-11-30 20:06:03 -07:00 |
tangxifan
|
58d4f1835c
|
[CI] Try to correct path when checking out OpenFPGA
|
2020-11-30 20:01:56 -07:00 |
tangxifan
|
e19201e9db
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[CI] Fix the wrong path to checkout OpenFPGA
|
2020-11-30 19:59:38 -07:00 |
tangxifan
|
cf8b83e271
|
[CI] Try another format of repo address
|
2020-11-30 19:53:54 -07:00 |
tangxifan
|
7cb188fc5c
|
[CI] Try to give a correct repo path
|
2020-11-30 19:52:14 -07:00 |
tangxifan
|
e66b2648da
|
[CI] Bug fix
|
2020-11-30 19:47:15 -07:00 |
tangxifan
|
54dbae1503
|
[CI] Try bug fix
|
2020-11-30 19:45:12 -07:00 |
tangxifan
|
6fe1609f91
|
[Test] Add CI test
|
2020-11-30 18:51:35 -07:00 |
tangxifan
|
e7fae9a32d
|
[Git] Remove submodules
|
2020-11-30 18:34:04 -07:00 |
tangxifan
|
e71b5eb3f4
|
[Git] add OpenFPGA as a submodule
|
2020-11-30 18:25:11 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
f4397e1656
|
Merge pull request #47 from LNIS-Projects/xt_dev
Bug fix in the arch port naming
|
2020-11-30 18:23:38 -07:00 |
tangxifan
|
be9399a016
|
[Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA
|
2020-11-30 17:58:56 -07:00 |
tangxifan
|
c1db942cc6
|
Merge pull request #46 from LNIS-Projects/tpagarani_dev
modify carry chain to change output mux
|
2020-11-30 13:57:56 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
0c5b378592
|
Merge pull request #45 from LNIS-Projects/xt_dev
Wrapper Testbench Converter
|
2020-11-30 11:44:00 -07:00 |
tangxifan
|
c676db1fe4
|
[Testbench] Bug fix in the ccff post-pnr testbench template
|
2020-11-30 11:18:42 -07:00 |
tangxifan
|
c638edfc14
|
[Testbench] Regenerate ccff/scff testbenches for wrapper
|
2020-11-30 10:33:50 -07:00 |
tangxifan
|
a900cba5a5
|
[HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail
|
2020-11-30 10:29:05 -07:00 |
tangxifan
|
e63cb7ca89
|
[Testbench] Rename testbench top module to be compatible with verification scripts
|
2020-11-30 10:23:30 -07:00 |
tangxifan
|
c70d5ac4f0
|
[Testbench] Add ccff test wrapper testbench and include netlist
|
2020-11-30 09:42:31 -07:00 |
tangxifan
|
2b40d5fb4b
|
[HDL] Bug fix
|
2020-11-30 09:34:26 -07:00 |
Tarachand Pagarani
|
9f7fb8a34d
|
modify carry chain to change output mux
|
2020-11-30 07:08:09 -08:00 |
tangxifan
|
fc3eadaf29
|
[Testbench] Add SCFF test for wrapper
|
2020-11-29 22:58:48 -07:00 |
tangxifan
|
0bf5a400e8
|
[Testbench] Add include netlists for wrapper testbenches
|
2020-11-29 22:48:25 -07:00 |
tangxifan
|
0ccc18d848
|
[Testbench] Bug fix in the paths to generate wrapper testbenches
|
2020-11-29 22:48:01 -07:00 |