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806 Commits

Author SHA1 Message Date
tangxifan 7d8812b844 [Script] Add missing QL synthesis arguments 2021-03-31 11:52:21 -06:00
tangxifan 7643950572 [Script] Fix the mismatched name of Quicklogic's yosys scripts in task configuration files 2021-03-31 10:54:10 -06:00
Andrew Pond c34d20824b added arch exploration files 2021-03-10 22:26:06 -07:00
tangxifan db791e1820
Merge pull request #98 from mithro/patch-1 
Fix spelling of floorplan.
 2021-02-13 15:48:09 -07:00
Tim Ansell 286ebc7da2
Fix spelling of floorplan. 2021-02-13 14:05:46 -08:00
Ganesh Gore a203d2aeee [DRCFix] Fixed filler cell boundary SOFA CHD 2021-02-10 23:29:18 -07:00
Ganesh Gore 7309d3822c [DRCFix] Fixed filler cell boundary 2021-02-10 22:43:08 -07:00
Ganesh Gore f8c34abb2f [DRCFix] Fixed filler cell boundary 2021-02-10 15:29:34 -07:00
Ganesh Gore 9091298772 [DRCfix] Used fill and decap cells as fillers 2021-02-09 16:27:46 -07:00
ganeshgore 5519215882
Merge pull request #95 from lnis-uofu/FPGA1212_QLSOFA_arch_typo 
Fix parsing error in FPGA1212_QLSOFA arch file.
 2021-02-09 08:29:46 -07:00
Ganesh Gore a1af3743ef [DRCfix] Swapped fill cell with decap 2021-02-08 22:58:28 -07:00
Ganesh Gore 3d9748aa17 [DRCfix] QLSOFA swapped fill cell with decap 2021-02-08 22:34:09 -07:00
Ganesh Gore bf96303eec [GDS] Replaced fill cells by decap cells 2021-02-08 17:26:58 -07:00
tpagarani aff48898e2
Merge pull request #94 from antmicro/comment-shift-reg 
Commented out shift_register mode in k4_N8 VPR architecture.
 2021-02-08 13:39:41 -05:00
tpagarani cbaf92f990
Merge pull request #96 from antmicro/k4_N8-io-reg-map-fix 
Fixed IO register pb_type map
 2021-02-08 13:38:59 -05:00
Maciej Kurc 0823e7e878 Corrected destination pb_type offsets for IO registers in k4_N8 OpenFPGA arch XML. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-08 10:41:48 +01:00
WRansohoff b4e3440972
Fix parsing error in FPGA1212_QLSOFA arch file. 
I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
 2021-02-05 11:36:29 -06:00
Maciej Kurc 63f210bc3d Commented out shift_register mode in k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-04 15:08:58 +01:00
tpagarani da52aa67eb
Merge pull request #91 from lnis-uofu/ql_ccff_dummy_stdcell_pointer 
(1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_anno…
 2021-02-04 01:06:01 -05:00
Kevin Liao 9318f0e49e Merge remote-tracking branch 'origin' into ql_ccff_dummy_stdcell_pointer 
For PR #91, in order to be merged to master, Xifan advise to merge with master.
 2021-02-03 20:25:50 -08:00
Lalit Narain Sharma c444e17588
Merge pull request #92 from antmicro/k4_N8-phy-primitives-fix 
Models and pb_types annotation for k4_N8 VPR architecture
 2021-02-03 17:01:43 +05:30
Maciej Kurc a6db672595 Fixed incorrect IREG pack-pattern 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Maciej Kurc 1e3490dc8d Added port relations to models and timing annotation to pb_types of the k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
tpagarani 4ea02f257a
Merge pull request #93 from lnis-uofu/ap3_test 
using default yosys script instead of custom script for multi_enc_dec…
 2021-02-03 05:00:48 -05:00
Lalit Sharma 0cdd94139f using default yosys script instead of custom script for multi_enc_decx2x4 design as custom script generated blif file is causing an assertion in openfpga. This is done temporarily to enable developers to checkin in SOFA, also requested Xifan to review this crash in openfpga. 2021-02-03 01:08:27 -08:00
Kevin Liao b5be7692c4 (1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_annotations 2021-01-29 08:56:59 -08:00
tpagarani 61655b8e1e
Merge pull request #90 from lnis-uofu/ql_ccff_dummy_stdcell_pointer 
SOFA branch ql_ccff_dummy_stdcell_pointer
 2021-01-26 23:04:50 -05:00
Kevin Liao 924b3d51de correct dummy stdcell verilog pointer 2021-01-26 15:45:59 -08:00
Kevin Liao 965fbdbfea correct to sky130_fd_sc_hd__sdfrtp_1 2021-01-26 15:36:33 -08:00
Kevin Liao f7feca6686 update header for description 2021-01-26 10:10:35 -08:00
Kevin Liao f0050b851d QuickLogic physical ccff 2021-01-26 09:43:53 -08:00
Kevin Liao 84c217bc56 replace CFGSDFFR with QL_CCFF and fix testbench related 2021-01-26 09:41:23 -08:00
liaokevin-ql d2240d8539
Merge pull request #86 from lnis-uofu/k4_N8_interface 
Merging registered/non-registered related IO definition in k4_N8 device
 2021-01-25 10:38:13 -08:00
Ganesh Gore 78e2a242b3 Merge remote-tracking branch 'origin/master' into ganesh_dev 2021-01-25 11:04:28 -07:00
Kevin Liao f1eb4c4f88 rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
Kevin Liao f7af0b40cf rename prefix for circuit_model iopad 2021-01-21 20:50:00 -08:00
Tarachand Pagarani 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names 2021-01-21 04:18:25 -08:00
tpagarani 658edb47f7
Merge pull request #89 from lnis-uofu/custom_yosys_scr 
Using custom yosys script for benchmarks run in generate_testbench task
 2021-01-21 06:58:01 -05:00
Lalit Sharma c34c777409 Using custom yosys script for benchmarks run in generate_testbench task 2021-01-20 21:18:38 -08:00
Tarachand Pagarani 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode 2021-01-20 01:16:59 -08:00
ganeshgore cbb7e020e8
Merge pull request #88 from lnis-uofu/xt_dev 
Minor fix on the waveform display for I/O circuitry
 2021-01-19 22:47:05 -07:00
Tarachand Pagarani 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-17 23:55:54 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
tangxifan d316f5cf21 Merge branch 'master' into xt_dev 2021-01-15 17:39:52 -07:00
tangxifan 851aa6e07d [Doc] Minor fix on the waveform display for I/O circuitry 2021-01-15 17:08:10 -07:00
Kevin Liao 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD 2021-01-15 12:48:32 -08:00
Kevin Liao f428234df8 correct EMBEDDED_IO_HD verilog pointer 2021-01-15 11:08:43 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
tpagarani 6f0dc05ffa
Merge pull request #87 from lnis-uofu/multiple_global_clocks 
add 4 global clocks
 2021-01-15 02:34:21 -05:00
Ganesh Gore 70d0ecdcac Added files to sync 2021-01-15 00:10:53 -07:00