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373 Commits 16 Branches 1 Tag 1.8 GiB
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373 Commits

Author SHA1 Message Date
tangxifan 0ccc18d848 [Testbench] Bug fix in the paths to generate wrapper testbenches 2020-11-29 22:48:01 -07:00
tangxifan 931b93b83d [Testbench] Now wrapper testbench conversion can be batched 2020-11-29 22:38:16 -07:00
tangxifan 12c3e157bf [Testbench] Add a tempo fix on the analog pins 2020-11-29 22:32:36 -07:00
tangxifan 50089e11f9 [Testbench] Bug fix 2020-11-29 22:20:15 -07:00
tangxifan 4b681b88a6 [Testbench] Fix the unconnected wbs_we_i pin 2020-11-29 22:17:10 -07:00
tangxifan 724696a661 [Testbench] Add missing ports in the wrapper 2020-11-29 22:16:04 -07:00
tangxifan 5235424e83 [Testbench] Adapt path for signal init in testbench converter 2020-11-29 21:44:29 -07:00
tangxifan fec19ebc55 [Testbench] Typo fix 2020-11-29 21:19:56 -07:00
tangxifan 951f5f84ee [Testbench] Typo fix 2020-11-29 21:15:36 -07:00
tangxifan 78addbe294 [HDL] Name fix to be compatible with testbench generation 2020-11-29 21:01:44 -07:00
tangxifan e3efcebf2b [Testbench] Bug fix in include netlist 2020-11-29 21:00:20 -07:00
tangxifan 4ab69d925c [Testbench] Add include netlist for wrapper testbench 2020-11-29 20:46:50 -07:00
tangxifan eeb904a3e3 [Testbench] Typo fix in wrapper testbench converter 2020-11-29 20:32:59 -07:00
tangxifan a414a600a6 [Testbench] Bug fixed in wrapper testbench generator 2020-11-29 20:31:19 -07:00
tangxifan 64ae33066e [Testbench] Add script to convert post-PnR testbench for wrapper testbench 2020-11-29 20:23:34 -07:00
tangxifan fcee5f1c91 [HDL] Typo fix in pin assignment description 2020-11-29 18:02:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) b0b5b0b325
Merge pull request #44 from LNIS-Projects/xt_dev 
Upgraded Caravel Wrapper Generator
 2020-11-29 13:27:52 -07:00
tangxifan de5411db6b [HDL] Add pin assignement for v1.1 HD FPGA 2020-11-29 12:58:53 -07:00
tangxifan cdfa3d5ff4 [HDL] Update wrapper using the new generator 2020-11-29 12:47:52 -07:00
tangxifan d0f9ca718d [HDL] bug fix in wrapper line generator 2020-11-29 12:47:22 -07:00
tangxifan 9f82d9bf54 [HDL] Correct typo in wrapper generator 2020-11-29 12:39:56 -07:00
tangxifan 899018d503 [HDL] Bug fix in wrapper template 2020-11-29 12:38:25 -07:00
tangxifan ea758cd5b1 [HDL] Update wrapper template as most codes can be auto-generated 2020-11-29 12:36:23 -07:00
tangxifan f78a53fd03 [HDL] Add tab to wrapper line generation 2020-11-29 12:35:24 -07:00
tangxifan ebd3053a4e [HDL] bug fix in wrapper generator 2020-11-29 12:31:32 -07:00
tangxifan 0e964534bc [HDL] bug fix in wrapper line generator 2020-11-29 12:01:15 -07:00
tangxifan 9622b44554 [HDL] Bug fix in JSON file syntax 2020-11-29 11:59:56 -07:00
tangxifan 27da78fe29 [HDL] Update wrapper line generator to parse json data 2020-11-29 11:57:34 -07:00
tangxifan 329b6644f3 [Script] Bug fix in creating directories for verification task 2020-11-29 11:02:23 -07:00
Ganesh Gore 20dc203b31 [FPGA1212_v1] Module level results 2020-11-29 11:02:17 -07:00
Ganesh Gore 225feaef3c [FPGA1212_v1] Added top-level pnr screenshots 2020-11-29 10:59:15 -07:00
tangxifan 4ec490645d Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-11-29 10:35:40 -07:00
tangxifan bc3d839e5b [HDL] Upgrading code generator for wrapper 2020-11-29 10:35:10 -07:00
tangxifan a50dfc09b5
Merge pull request #43 from LNIS-Projects/ganesh_dev 
[FPGA1212_V1] Updated design
 2020-11-29 10:34:29 -07:00
Ganesh Gore 7db7c240e3 [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed 2020-11-29 10:24:03 -07:00
tangxifan aac8ddc3ec [HDL] update json to ease parsing 2020-11-28 21:10:46 -07:00
tangxifan 47389a483e [HDL] Add json description for pin assignment v1.0 2020-11-28 20:55:41 -07:00
tangxifan 54eb5b469b [Doc] Fix pin direction typo in I/O resource map 2020-11-28 20:13:05 -07:00
tangxifan aff43bf473 [Doc] Add README to HDL common files 2020-11-28 17:37:36 -07:00
Laboratory for Nano Integrated Systems (LNIS) 90f4e3fa70
Merge pull request #42 from LNIS-Projects/xt_dev 
Push-button Modelsim Verification for Specific FPGA fabric
 2020-11-28 16:44:21 -07:00
tangxifan 969ef7976f [Testbench] Remove those with problems in convergence 2020-11-28 15:24:54 -07:00
tangxifan 3c685311e9 [Testbench] Bug fix for the ccff testbench to sync with latest netlist 2020-11-28 15:22:50 -07:00
tangxifan 4e9b07125e [Script] Bug fix 2020-11-28 15:01:09 -07:00
tangxifan d70bcbb7ca [Doc] Add README for Modelsim workspace 2020-11-28 14:59:26 -07:00
tangxifan d3b1562fa2 [Testbench] Rename top-level module to be compatible to Modelsim task run scripts 2020-11-28 14:55:17 -07:00
tangxifan ee92b15f0e [Script] Bug fix in modelsim task-run script 2020-11-28 14:50:39 -07:00
tangxifan 2380783808 [Testbench] Remove post pnr testbenches that can be auto-generated 2020-11-28 14:46:27 -07:00
tangxifan 8374fcfd4e [Script] Rectify output messages 2020-11-28 14:41:48 -07:00
tangxifan 396988b1b6 [Script] Now testbench generator requires a specific dir name 2020-11-28 14:39:18 -07:00
tangxifan e88a33831c [Testbench] Update scripts to rename top-level module for post-PnR testbenches 2020-11-28 14:29:56 -07:00