20 Commits

Author	SHA1	Message	Date
Ganesh Gore	4ab8440233	Fixed architecture files for new OpenFPGA version	2023-03-01 22:31:24 -07:00
romangauchi	568de2497b	[SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'	2022-01-31 11:36:42 -07:00
tangxifan	51a00d4612	Merge branch 'master' into xt_dev	2021-06-09 19:42:36 -06:00
tangxifan	d15e7db1be	[Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench'	2021-06-09 19:40:41 -06:00
Ganesh Gore	7d4b57da04	[SOFA] Updated task configuration	2021-05-31 12:05:36 -06:00
Ganesh Gore	57245e9a77	[SOFA1212] Updated SOFA Project	2021-04-05 23:29:01 -06:00
Ganesh Gore	3a472b0db0	[Flow] Adding Makefile for running task	2021-04-03 17:54:59 -06:00
Ganesh Gore	f8c34abb2f	[DRCFix] Fixed filler cell boundary	2021-02-10 15:29:34 -07:00
Ganesh Gore	9091298772	[DRCfix] Used fill and decap cells as fillers	2021-02-09 16:27:46 -07:00
Ganesh Gore	bf96303eec	[GDS] Replaced fill cells by decap cells	2021-02-08 17:26:58 -07:00
Lalit Sharma	51f11ee630	Replacing deprecated tile_port syntax	2021-01-12 21:33:53 -08:00
Ganesh Gore	6ef27d5399	[Cleanup] Removed old task and verilog directories	2020-12-20 10:50:13 -07:00
Ganesh Gore	c36e8d797a	Updated all the results	2020-12-20 03:44:00 -07:00
Ganesh Gore	55acf06335	Updated design with new GDS nad updated verilog netlist	2020-12-20 03:31:26 -07:00
Ganesh Gore	da4ae780a9	[Cleanup] Converted .spef to .spef.gz	2020-12-20 02:10:51 -07:00
Ganesh Gore	84ab1ac17f	[SOFA_HD] Minor updates + Added labels for LVS Fix + One metal shape correction	2020-12-15 08:46:51 -07:00
Ganesh Gore	13fc082cb3	[SOFA_HD] Updated verification script	2020-12-14 01:16:30 -07:00
Ganesh Gore	5c12369380	[SOFA_HD] Updated netlist + Caravel precheck passed	2020-12-14 01:16:00 -07:00
Ganesh Gore	967905e046	[SOFA_HD] Updated netlist and task	2020-12-14 01:14:14 -07:00
Ganesh Gore	fa87753d62	[Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD	2020-12-14 00:45:11 -07:00