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[SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'

This commit is contained in:
romangauchi 2022-01-31 11:34:26 -07:00
parent 250aafe02d
commit 568de2497b
2 changed files with 2 additions and 2 deletions
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2
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga
View File

@ -54,7 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge

2
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga
View File

@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge