[SOFA_PLUS] fix the default OpenFPGA task testbench/simulation

This commit is contained in:
romangauchi 2022-01-30 22:29:32 -07:00
parent 47b839fa0a
commit 250aafe02d
2 changed files with 38 additions and 1 deletions

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@ -0,0 +1,37 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 1*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=60
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
[SYNTHESIS_PARAM]
bench0_top = counter
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

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@ -45,7 +45,7 @@ write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
write_full_testbench --file ./SRC \
--bitstream fabric_bitstream.bit
--bitstream fabric_bitstream.bit \
--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
--explicit_port_mapping