From 568de2497bd0b971042685ff4c40b9d086275dbd Mon Sep 17 00:00:00 2001 From: romangauchi Date: Mon, 31 Jan 2022 11:34:26 -0700 Subject: [PATCH] [SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error' --- .../FPGA1212_SOFA_CHD_task/generate_testbench.openfpga | 2 +- .../FPGA1212_SOFA_HD_task/generate_testbench.openfpga | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga index 59b4638..83a16c1 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga @@ -54,7 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga index 49a224f..64d6fcc 100644 --- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga @@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge