19 Commits

Author	SHA1	Message	Date
Ganesh Gore	4ab8440233	Fixed architecture files for new OpenFPGA version	2023-03-01 22:31:24 -07:00
romangauchi	568de2497b	[SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'	2022-01-31 11:36:42 -07:00
tangxifan	d15e7db1be	[Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench'	2021-06-09 19:40:41 -06:00
Ganesh Gore	1b2a14886b	[Repo] Adding skywater PDK as submodule	2021-04-06 08:58:07 -06:00
Ganesh Gore	da95b57b6b	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
Ganesh Gore	3a472b0db0	[Flow] Adding Makefile for running task	2021-04-03 17:54:59 -06:00
Ganesh Gore	a203d2aeee	[DRCFix] Fixed filler cell boundary SOFA CHD	2021-02-10 23:29:18 -07:00
Ganesh Gore	a1af3743ef	[DRCfix] Swapped fill cell with decap	2021-02-08 22:58:28 -07:00
Lalit Sharma	51f11ee630	Replacing deprecated tile_port syntax	2021-01-12 21:33:53 -08:00
Ganesh Gore	562641ed4d	[SOFA-CHD] Bugfix to fix floating cin net	2020-12-22 00:23:12 -07:00
Ganesh Gore	55acf06335	Updated design with new GDS nad updated verilog netlist	2020-12-20 03:31:26 -07:00
Ganesh Gore	da4ae780a9	[Cleanup] Converted .spef to .spef.gz	2020-12-20 02:10:51 -07:00
Ganesh Gore	d7f36a1f70	[SOFA-CHD] Updated SOFA-CHD - Updated cells - DRC Clean	2020-12-16 15:00:15 -07:00
Ganesh Gore	9f9897c5e2	[SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending	2020-12-14 00:34:42 -07:00
Ganesh Gore	0672f01e3a	[Cleanup] Removed unused SDCs	2020-12-14 00:31:03 -07:00
Ganesh Gore	77bb6d4eae	[SOFA_CHD] Added Verification results	2020-12-09 00:55:27 -07:00
Ganesh Gore	45ff6d2dfe	[SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF	2020-12-09 00:54:03 -07:00
Ganesh Gore	1a2e6de718	[SOFA_CHD] Removed large testbench file	2020-12-09 00:51:30 -07:00
Ganesh Gore	9284bbf8fa	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00