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116 Commits

Author SHA1 Message Date
Andrew Pond 3dcdad3253 updated to use timing annotation file 2021-04-06 08:12:34 -06:00
Andrew Pond 9ba10b3700 Merge branch 'master' into arch_exploration 2021-04-05 08:52:14 -06:00
tangxifan 2bbce2b92f [Arch] Update timing for CHD 2021-04-03 17:46:53 -06:00
tangxifan 7d1d6517fb [Arch] Update timing annotation for LUTs 2021-04-03 14:33:39 -06:00
Andrew Pond 1fc9e0574c Merge branch 'master' into arch_exploration 
Merge master fix into branch
 2021-04-03 11:38:01 -06:00
tangxifan 0838b48dec [Doc] Add timing and detailed routing arch to documentation 2021-04-02 18:46:43 -06:00
tangxifan 8196514c26 [Arch] Bug fix 2021-04-01 22:16:44 -06:00
tangxifan b22584e7a1 [MISC] Bug fixes for wrong paths in task configuration files; typo in arch files 2021-04-01 21:16:08 -06:00
tangxifan 7059c6a014 [Arch] Add timing variables for CHD arch but will update later 2021-04-01 21:05:53 -06:00
tangxifan 36b871bcbb [Arch] Name change for FF CLK2Q vairable 2021-04-01 21:00:53 -06:00
tangxifan cf6bdf0768 [Arch] Update QLSOFA arch with timing variables 2021-04-01 21:00:09 -06:00
tangxifan c9b4699508 [Arch] Add QLSOFA timing at TT corner 2021-04-01 20:59:47 -06:00
tangxifan 881d07a123 [Arch] Bug fix 2021-04-01 20:43:24 -06:00
tangxifan 2afd42bb45 [Arch] Explicit comment SOFA HD arch 2021-04-01 20:31:13 -06:00
tangxifan 54df2a4f97 [Arch] Update SOFA HD arch to use timing variables 2021-04-01 20:29:13 -06:00
tangxifan f28ff97b8b [Arch] Move timing values to design variable yml so that we can reuse arch XML to model timing in different corners 2021-04-01 20:28:38 -06:00
tangxifan 062120ffd9 [Arch] Update timing for SOFA architecture 2021-04-01 16:39:19 -06:00
Andrew Pond c34d20824b added arch exploration files 2021-03-10 22:26:06 -07:00
tpagarani aff48898e2
Merge pull request #94 from antmicro/comment-shift-reg 
Commented out shift_register mode in k4_N8 VPR architecture.
 2021-02-08 13:39:41 -05:00
Maciej Kurc 0823e7e878 Corrected destination pb_type offsets for IO registers in k4_N8 OpenFPGA arch XML. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-08 10:41:48 +01:00
Maciej Kurc 63f210bc3d Commented out shift_register mode in k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-04 15:08:58 +01:00
Kevin Liao 9318f0e49e Merge remote-tracking branch 'origin' into ql_ccff_dummy_stdcell_pointer 
For PR #91, in order to be merged to master, Xifan advise to merge with master.
 2021-02-03 20:25:50 -08:00
Maciej Kurc a6db672595 Fixed incorrect IREG pack-pattern 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Maciej Kurc 1e3490dc8d Added port relations to models and timing annotation to pb_types of the k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Kevin Liao b5be7692c4 (1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_annotations 2021-01-29 08:56:59 -08:00
Kevin Liao 924b3d51de correct dummy stdcell verilog pointer 2021-01-26 15:45:59 -08:00
Kevin Liao 84c217bc56 replace CFGSDFFR with QL_CCFF and fix testbench related 2021-01-26 09:41:23 -08:00
Kevin Liao f7af0b40cf rename prefix for circuit_model iopad 2021-01-21 20:50:00 -08:00
Tarachand Pagarani 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names 2021-01-21 04:18:25 -08:00
Tarachand Pagarani 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode 2021-01-20 01:16:59 -08:00
Tarachand Pagarani 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-17 23:55:54 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
Kevin Liao 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD 2021-01-15 12:48:32 -08:00
Kevin Liao f428234df8 correct EMBEDDED_IO_HD verilog pointer 2021-01-15 11:08:43 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
Kevin Liao 806303af11 remove soft_adder, and fix Test_en from ccff 2021-01-14 20:14:04 -08:00
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation 2021-01-13 00:48:03 -08:00
Lalit Sharma 6702de4516 Merging latest changes from master related to tile_port deprecation 2021-01-12 22:33:04 -08:00
Lalit Sharma 51f11ee630 Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Kevin Liao e06fdd0a48 add annotation to support soft_adder mode 2021-01-12 21:21:53 -08:00
Kevin Liao 489e370390 init 2021-01-11 21:11:12 -08:00
Lalit Sharma 8f1bdc2e87 Updating interface definition for QL k4_N8 device 2021-01-11 23:20:49 +05:30
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00
Tarachand Pagarani 61facff870 fix the carry in dangling and carry out accessible to regular routing 2020-12-29 18:54:48 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00