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simulation_info_writer.cpp
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now make ini file generation more flexible: user can specify a name or use the default name
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2019-11-13 12:55:57 -07:00 |
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simulation_info_writer.h
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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verilog_api.cpp
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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verilog_api.h
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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verilog_auxiliary_netlists.cpp
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refactoring Verilog simulation flag generations
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2019-11-05 13:45:11 -07:00 |
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verilog_auxiliary_netlists.h
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refactoring Verilog simulation flag generations
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2019-11-05 13:45:11 -07:00 |
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verilog_decoders.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_decoders.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_essential_gates.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_essential_gates.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_formal_random_top_testbench.cpp
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_formal_random_top_testbench.h
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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verilog_global.c
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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verilog_global.h
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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verilog_grid.cpp
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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verilog_grid.h
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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verilog_lut.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_lut.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_memory.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_memory.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_module_writer.cpp
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critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
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2019-11-08 15:01:30 -07:00 |
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verilog_module_writer.h
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
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verilog_mux.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_mux.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_preconfig_top_module.cpp
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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verilog_preconfig_top_module.h
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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verilog_routing.cpp
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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verilog_routing.h
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remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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verilog_submodule_utils.cpp
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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verilog_submodule_utils.h
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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verilog_submodules.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_submodules.h
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
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verilog_testbench_utils.cpp
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_testbench_utils.h
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_top_module.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_top_module.h
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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verilog_top_testbench.cpp
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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verilog_top_testbench.h
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_wire.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_wire.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_writer_utils.cpp
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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verilog_writer_utils.h
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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