OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
..
verilog_api.c Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
verilog_api.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_autocheck_top_testbench.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_autocheck_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_compact_netlist.c Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_compact_netlist.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_decoder.c fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
verilog_decoder.h add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
verilog_formal_random_top_testbench.c Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
verilog_formal_random_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_formality_autodeck.c cleaned unused variables 2019-05-13 14:45:02 -06:00
verilog_formality_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_global.c Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
verilog_global.h Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
verilog_include_netlists.c add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
verilog_include_netlists.h add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
verilog_modelsim_autodeck.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_modelsim_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_pbtypes.c Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_pbtypes.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_primitives.c Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_primitives.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_report_timing.c Correction pre-merge 2019-06-27 14:33:06 -06:00
verilog_report_timing.h updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
verilog_routing.c Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_routing.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_sdc.c keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
verilog_sdc.h Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
verilog_sdc_pb_types.c Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
verilog_sdc_pb_types.h clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
verilog_submodules.c Done with the submodules 2019-07-01 14:24:09 -06:00
verilog_submodules.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_tcl_utils.c fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
verilog_tcl_utils.h fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
verilog_top_netlist_utils.c Stable, unfinished 2019-06-26 16:54:41 -06:00
verilog_top_netlist_utils.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_top_testbench.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_utils.c Further add new functions to tree 2019-07-01 12:12:36 -06:00
verilog_utils.h Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
verilog_verification_top_netlist.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_verification_top_netlist.h clean warnings 2019-05-24 16:48:08 -06:00