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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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f189ef1d8f
OpenFPGA
/
vpr7_x2p
/
vpr
/
SRC
/
fpga_x2p
History
Baudouin Chauviere
f189ef1d8f
Done with the submodules
2019-07-01 14:24:09 -06:00
..
base
Include new files in the parameter spreading
2019-07-01 11:27:48 -06:00
bitstream
critical bug fixed in bitstream generator for compact routing hierarchy
2019-06-26 15:51:11 -06:00
clb_pin_remap
cleaned unused variables
2019-05-13 14:45:02 -06:00
router
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
2019-06-15 12:23:36 -06:00
shell
Merge branch 'multimode_clb' of
https://github.com/LNIS-Projects/OpenFPGA
into multimode_clb
2019-05-13 14:45:57 -06:00
spice
fix a bug for iopad SPICE generation
2019-06-11 11:43:56 -06:00
verilog
Done with the submodules
2019-07-01 14:24:09 -06:00