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fabric_verilog_options.cpp
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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fabric_verilog_options.h
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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verilog_api.cpp
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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verilog_api.h
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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verilog_auxiliary_netlists.cpp
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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verilog_auxiliary_netlists.h
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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verilog_constants.h
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[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
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verilog_decoders.cpp
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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verilog_decoders.h
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_essential_gates.cpp
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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verilog_essential_gates.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_formal_random_top_testbench.cpp
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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verilog_formal_random_top_testbench.h
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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verilog_grid.cpp
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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verilog_grid.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_lut.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_lut.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_memory.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_memory.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_module_writer.cpp
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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verilog_module_writer.h
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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verilog_mux.cpp
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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verilog_mux.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_port_types.h
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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verilog_preconfig_top_module.cpp
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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verilog_preconfig_top_module.h
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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verilog_routing.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_routing.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_simulation_info_writer.cpp
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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verilog_simulation_info_writer.h
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_submodule.cpp
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_submodule.h
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_submodule_utils.cpp
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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verilog_submodule_utils.h
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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verilog_testbench_options.cpp
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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verilog_testbench_options.h
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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verilog_testbench_utils.cpp
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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verilog_testbench_utils.h
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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verilog_top_module.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_top_module.h
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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verilog_top_testbench.cpp
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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verilog_top_testbench.h
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[Tool] Avoid outputting signal initialization codes because they are bulky
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2020-12-06 14:29:16 -07:00 |
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verilog_wire.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_wire.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_writer_utils.cpp
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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verilog_writer_utils.h
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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