tangxifan 8c311b8282 [Tool] Bug fix in repacker for considering design constraints		2021-01-17 12:26:14 -07:00
..
annotation	[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation	2021-01-15 12:01:53 -07:00
base	[Tool] Start deploying design constraints in repack engine	2021-01-16 21:27:12 -07:00
fabric	[Tool] Bug fix in creating multi-bit clock port connections	2021-01-12 18:38:00 -07:00
fpga_bitstream	[Tool] Upgrade openfpga to support extended global tile port definition	2021-01-09 18:47:12 -07:00
fpga_sdc	[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation	2021-01-15 12:01:53 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation	2021-01-15 12:01:53 -07:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[Tool] Bug fix in repacker for considering design constraints	2021-01-17 12:26:14 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Upgrade openfpga to support extended global tile port definition	2021-01-09 18:47:12 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00