AurelienAlacchi 3f5cc59c0a Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) ... * Add required files for LUTRAM integration and testing * Add task for lutram * Repair format (tab and space mismatched) * Add disclaimer in architecture file Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>		2021-01-29 10:19:05 -07:00
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MCNC_Verilog	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
mcnc_big20	add explicit port mapping support in testbenches; remove dangling ports in benchmarks	2019-11-02 23:03:47 -06:00
micro_benchmark	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
pipelined_8bit_adder	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
test_modes	add single mode test case to regression test. debugging now	2019-10-28 15:57:17 -06:00