AurelienAlacchi 3f5cc59c0a Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) ... * Add required files for LUTRAM integration and testing * Add task for lutram * Repair format (tab and space mismatched) * Add disclaimer in architecture file Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>		2021-01-29 10:19:05 -07:00
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FSM_three_code	enrich micro benchmarks	2020-07-22 12:33:52 -06:00
RISC_posedge_clk	add regression test to track runtime on big fpga devices using practical benchmarks	2020-07-28 12:38:42 -06:00
SAPone	add regression test to track runtime on big fpga devices using practical benchmarks	2020-07-28 12:38:42 -06:00
and2	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
and2_latch	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
and2_or2	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
and2_pipelined	[Benchmark] Bug fix in pipelined and2 benchmark	2021-01-10 10:27:59 -07:00
asyn_spram_4x1	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
counter	bug fix in the regression test due to benchmark changes	2020-07-22 13:17:05 -06:00
counter4bit_2clock	[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock	2021-01-13 15:43:31 -07:00
or2	bug fix in read architecture bitstream and regression tests	2020-07-27 19:37:05 -06:00
routing_test	bug fixed in routing_test.v. Deployed to regression tests	2020-06-11 19:31:01 -06:00
syn_spram_4x1	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
test_mode_low	Added test_mode_low benchmark	2020-06-11 19:31:01 -06:00