tangxifan baa2c6b7ef update arch to support reset signal for SRAm		2020-06-11 19:31:14 -06:00
..
adder.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
aib.v	try to add aib test case. bug found	2020-04-12 14:54:45 -06:00
config_latch.v	frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops	2020-06-11 19:31:11 -06:00
dpram.v	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
dpram16k.v	add test case of BRAM to Travis CI	2020-04-12 14:27:05 -06:00
dpram_tb.v	Adding DPRAM behavioural Verilog netlist and its TB	2019-12-03 13:58:20 -07:00
ff.v	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
ff_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
io.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
lb_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
lut6.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
mux2.v	bug fixed for std cell MUX2 architecture and add the case to regression tests	2019-11-06 16:06:47 -07:00
mux_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
sram.v	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
sram_tb.v	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00