16 lines
347 B
Verilog
16 lines
347 B
Verilog
//-----------------------------------------------------
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// Design Name : lut6
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// File Name : lut6.v
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// Function : 6-input Look Up Table
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// Coder : Xifan TANG
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//-----------------------------------------------------
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module lut6 (
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input [5:0] in,
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output out,
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input [63:0] sram,
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input [63:0] sram_inv);
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assign out = sram[in];
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endmodule
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