OpenFPGA/openfpga_flow/openfpga_shell_scripts
Jingrong Lin 77b188060b
Merge branch 'master' into preloading_clean
2024-09-11 11:08:49 +08:00
..
auto_bus_group_example_script.openfpga
behavioral_verilog_example_script.openfpga
bitstream_setting_example_script.openfpga
bitstream_setting_pbPinFixup_example_script.openfpga
configuration_chain_example_script.openfpga
custom_fabric_netlist_example_script.openfpga
duplicated_grid_pin_example_script.openfpga
example_clkntwk_full_tb_script.openfpga [test] add extra options to route clock rr_graph command in examples 2024-06-28 13:39:41 -07:00
example_clkntwk_int_driver_no_ace_script.openfpga [test] reworking the testcase to validate clock network with internal drivers 2024-07-10 11:36:22 -07:00
example_clkntwk_no_ace_script.openfpga [test] add extra options to route clock rr_graph command in examples 2024-06-28 13:39:41 -07:00
example_clkntwk_pb_pin_fixup_no_ace_script.openfpga [test] add a new testcase to validate mapping gnet to msb during pb_pin_fix 2024-09-09 13:54:20 -07:00
example_clkntwk_script.openfpga [test] add extra options to route clock rr_graph command in examples 2024-06-28 13:39:41 -07:00
example_script.openfpga
example_without_ace_script.openfpga
external_file_for_source_example_script.openfpga
fast_configuration_example_script.openfpga
fix_device_const_undriven_net_example_script.openfpga [test] add new tests to validate the options for undriven inputs in verilog netlists 2024-08-06 20:58:00 -07:00
fix_device_example_script.openfpga
fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
fix_device_global_tile_clock_example_script.openfpga
fix_device_pbPinFixup_example_script.openfpga
fix_device_route_chan_width_example_script.openfpga
fix_heterogeneous_device_example_script.openfpga
fix_heterogeneous_device_pbPinFixup_example_script.openfpga
fix_pins_example_script.openfpga
flatten_routing_example_script.openfpga
fpga_core_example_script.openfpga
full_testbench_bus_group_example_script.openfpga
full_testbench_example_script.openfpga
full_testbench_example_without_ace_script.openfpga
full_testbench_without_self_checking_example_script.openfpga
generate_bitstream_example_script.openfpga
generate_bitstream_fix_device_example_script.openfpga
generate_bitstream_fpga_core_example_script.openfpga
generate_bitstream_global_tile_multiclock_example_script.openfpga
generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
generate_fabric_example_script.openfpga
generate_fabric_key_example_script.openfpga
generate_secure_fabric_example_script.openfpga
generate_secure_fabric_from_key_example_script.openfpga
generate_spice_example_script.openfpga
generate_testbench_example_script.openfpga
global_tile_clock_example_script.openfpga
global_tile_clock_full_testbench_example_script.openfpga [test] create a new example script for fixed routing W case 2024-05-07 10:24:15 -07:00
global_tile_clock_full_testbench_fix_routeW_example_script.openfpga [test] create a new example script for fixed routing W case 2024-05-07 10:24:15 -07:00
global_tile_clock_options_full_testbench_example_script.openfpga [core] fixed some bugs 2023-09-25 22:27:24 -07:00
global_tile_clock_pbPinFixup_example_script.openfpga
global_tile_multiclock_example_script.openfpga
group_config_block_full_testbench_example_script.openfpga [core] a new test to validate the L shape in homo geneous fpga 2023-08-11 13:05:46 -07:00
group_config_block_preconfig_testbench_example_script.openfpga [test] add options to write fabric hierarchy file 2024-05-02 22:00:47 -07:00
group_tile_clkntwk_preconfig_testbench_example_script.openfpga [test] add a new test to validate clock network on module named by index 2024-07-30 14:06:53 -07:00
group_tile_full_testbench_example_script.openfpga [test] disable pnr writer in test cases 2023-07-25 15:39:25 -07:00
group_tile_preconfig_testbench_example_script.openfpga [test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules 2023-07-27 17:03:02 -07:00
group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga [test] now test regex as module name for fabric pin physical location 2024-04-11 15:01:19 -07:00
ignore_global_nets_on_pins_example_script.openfpga
implicit_verilog_example_script.openfpga
iverilog_example_script.openfpga
iwls_benchmark_example_script.openfpga
load_external_arch_bitstream_example_script.openfpga
local_clk_gen_example_script.openfpga
mcnc_example_script.openfpga
mock_wrapper_example_script.openfpga
module_rename_full_testbench_example_script.openfpga [test] add a new test to validate module renaming using index 2023-09-16 17:55:52 -07:00
module_rename_preconfig_testbench_example_script.openfpga [test] add a new test to validate renaming rules 2023-09-17 13:29:12 -07:00
no_time_stamp_example_script.openfpga [test] fixed a bug and add golden outputs 2024-05-02 22:07:22 -07:00
pbPinFixup_example_script.openfpga
pin_constrain_example_script.openfpga
preconfig_fabric_example_script.openfpga
preconfigured_testbench_bus_group_example_script.openfpga
preconfigured_testbench_no_time_stamp_example_script.openfpga
preconfigured_testbench_relative_path_example_script.openfpga
preconfigured_testbench_without_self_checking_example_script.openfpga
preload_rr_graph_example_script.openfpga [test] add new tests to verify rr graph preloading in two file formats 2024-05-09 23:10:45 -07:00
quicklogic_flow_example_script.openfpga
read_unique_blocks_example_script.openfpga add preload flag to device_rr_gsb and revert change to build fabric 2024-08-28 18:14:33 +08:00
read_unique_blocks_full_flow_example_script.openfpga add test case 2024-08-30 14:17:42 +08:00
read_write_unique_blocks_full_flow_example_script.openfpga add a task case to ease the use of compress_routing option 2024-09-09 14:18:47 +08:00
rename_scripts.sh
report_bitstream_distribution_example_script.openfpga
report_reference_example_script.openfpga Add more test cases and update documentation about the YAML file format of this command 2024-09-09 17:49:10 +08:00
sdc_time_unit_example_script.openfpga
skywater_tapeout_example_script.openfpga
source_file_example_script.openfpga
source_string_example_script.openfpga
verilog_default_net_type_example_script.openfpga
vpr_standalone_example_script.openfpga
vtr_benchmark_example_script.openfpga
wire_lut_example_script.openfpga
write_full_testbench_dont_care_bits_example_script.openfpga
write_full_testbench_example_script.openfpga
write_full_testbench_fpga_core_example_script.openfpga
write_full_testbench_relative_path_example_script.openfpga
write_full_testbench_simulator_support_example_script.openfpga [test] debug 2023-12-08 13:52:52 -08:00
write_gsb_example_script.openfpga
write_io_mapping_example_script.openfpga
write_testbench_template_example_script.openfpga [test] add a new test case to validate the new feature 2023-11-02 21:08:36 -07:00
write_unique_blocks_example_script.openfpga add test case 2024-08-26 02:45:57 -07:00
write_unique_blocks_full_flow_example_script.openfpga add test case 2024-08-30 14:17:42 +08:00