Andrew Pond 8c38747d6c revised PR		2021-12-16 09:53:16 -07:00
..
FIR_filter	[Benchmark] Add micro benchmark for FIR filter	2021-02-18 19:37:44 -07:00
FSM_three_code	enrich micro benchmarks	2020-07-22 12:33:52 -06:00
RISC_posedge_clk	add regression test to track runtime on big fpga devices using practical benchmarks	2020-07-28 12:38:42 -06:00
SAPone	add regression test to track runtime on big fpga devices using practical benchmarks	2020-07-28 12:38:42 -06:00
adder	revised PR	2021-12-16 09:53:16 -07:00
and2	[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture	2021-02-09 15:41:21 -07:00
and2_latch	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
and2_latch_2clock	[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs	2021-04-21 14:03:51 -06:00
and2_or2	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
and2_pipelined	[Benchmark] Bug fix in pipelined and2 benchmark	2021-01-10 10:27:59 -07:00
and4	[HDL] Add more micro benchmarks for counter, and-gate and mac unit	2021-06-21 16:48:35 -06:00
asyn_spram_4x1	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
blinking	[Benchmark] Add microbenchmark 1-bit blinking	2021-05-06 15:17:27 -06:00
config_loader	added signal gen regression test to shell script	2021-06-30 16:18:09 -06:00
counters	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
dual_port_ram_1k	[Benchmark] Add 1k DPRAM benchmark which can fit new arch	2021-04-28 11:26:31 -06:00
dual_port_ram_16k	[Benchmark] Bug fix in dual port ram 16k benchmark	2021-04-27 23:33:20 -06:00
fifo/rtl	[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised	2021-04-27 22:09:10 -06:00
mac	[HDL] Add more micro benchmarks for counter, and-gate and mac unit	2021-06-21 16:48:35 -06:00
or2	bug fix in read architecture bitstream and regression tests	2020-07-27 19:37:05 -06:00
pipelined_8bit_adder	[Benchmark] move benchmarks to microbenchmark category	2021-04-27 22:12:30 -06:00
routing_test	bug fixed in routing_test.v. Deployed to regression tests	2020-06-11 19:31:01 -06:00
signal_gen	fixed tab spacing	2021-07-01 16:42:04 -06:00
syn_spram_4x1	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
test_mode_low	Added test_mode_low benchmark	2020-06-11 19:31:01 -06:00
test_modes	[Benchmark] move benchmarks to microbenchmark category	2021-04-27 22:12:30 -06:00