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verilog_api.c
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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verilog_api.h
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_autocheck_tb.c
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Add security in checking to avoid simulation glitch error
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2018-12-10 09:46:16 -07:00 |
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verilog_autocheck_tb.h
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
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verilog_decoder.c
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Correct sub_modules.v generation to include decoders.v when necessary
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2018-12-05 13:52:25 -07:00 |
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verilog_decoder.h
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_global.c
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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verilog_global.h
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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verilog_lut.c
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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verilog_lut.h
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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verilog_modelsim_autodeck.c
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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verilog_modelsim_autodeck.h
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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verilog_pbtypes.c
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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verilog_pbtypes.h
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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verilog_primitives.c
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_primitives.h
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_routing.c
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_routing.h
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |
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verilog_submodules.c
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Add possibility to choose default value for initialization
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2018-12-06 15:34:14 -07:00 |
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verilog_submodules.h
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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verilog_top_netlist.c
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Edit waveform generator + fix clock mapping in autochecked testbench
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2018-12-09 15:48:59 -07:00 |
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verilog_top_netlist.h
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
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verilog_utils.c
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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verilog_utils.h
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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