tangxifan 72fbd8d6a8 update blif reader to identify clock signals		2018-12-10 13:28:44 -07:00
..
base	update blif reader to identify clock signals	2018-12-10 13:28:44 -07:00
clb_pin_remap	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
spice	fix bugs for wired LUTs	2018-11-27 12:46:30 -07:00
verilog	Add security in checking to avoid simulation glitch error	2018-12-10 09:46:16 -07:00