tangxifan 72fbd8d6a8 update blif reader to identify clock signals		2018-12-10 13:28:44 -07:00
..
libarchfpga	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
pcre	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
printhandler	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
tech	Update on the examples to respect the new syntax	2018-11-19 15:50:29 -07:00
vpr	update blif reader to identify clock signals	2018-12-10 13:28:44 -07:00
Makefile	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00