tangxifan 72fbd8d6a8 update blif reader to identify clock signals		2018-12-10 13:28:44 -07:00
..
ARCH	Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)	2018-12-08 22:57:54 -07:00
Circuits	Edit waveform generator + fix clock mapping in autochecked testbench	2018-12-09 15:48:59 -07:00
SRC	update blif reader to identify clock signals	2018-12-10 13:28:44 -07:00
SpiceNetlists	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
VerilogNetlists	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
picorv	Changed for the naming	2018-12-08 16:19:38 -07:00
Makefile	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
go.sh	add a section for picorv generation through the flow	2018-12-08 11:33:14 -07:00
picorv.sh	Changed for the naming	2018-12-08 16:19:38 -07:00