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adder.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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aib.v
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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config_latch.v
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[Architecture] Patch Verilog HDL for configurable latch
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2020-09-23 17:21:30 -06:00 |
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config_latch_neg_rst.v
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[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
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2020-09-23 17:19:02 -06:00 |
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dpram.v
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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dpram1k.v
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[Architecture] Add verilog HDL for dual-port BRAM 1k
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2020-09-22 12:23:28 -06:00 |
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dpram16k.v
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
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dpram_tb.v
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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ff.v
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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ff_en.v
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[Architecture] Patch DFF Verilog HDL
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2020-09-23 17:52:59 -06:00 |
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ff_tb.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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frac_mem_32k.v
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add Verilog design for fracturable 32k memory
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2020-08-18 21:13:46 -06:00 |
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io.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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lb_tb.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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lut6.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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mult_32x32.v
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[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
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2020-09-22 15:15:19 -06:00 |
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mult_36x36.v
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add 36-bit fracturable multiplier Verilog
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2020-08-18 14:06:08 -06:00 |
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mux2.v
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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mux_tb.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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sram.v
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update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
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sram_tb.v
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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