tangxifan c87dbc4880 start using counter benchmark in regression tests		2020-06-11 19:31:15 -06:00
..
OpenFPGAShellScripts	add fast configuration test case for memory bank configuration protocol	2020-06-11 19:31:14 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
arch	bug fixed in k6_n10_40 architecture	2020-06-11 19:31:15 -06:00
benchmarks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
scripts	Added support for simulation setting file in the task flow	2020-06-11 19:28:13 -06:00
tasks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00