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k4_N4_40nm_bank_openfpga.xml
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update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
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k4_N4_40nm_cc_openfpga.xml
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start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
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2020-06-11 19:31:10 -06:00 |
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k4_N4_40nm_fixed_sim_openfpga.xml
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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k4_N4_40nm_frame_openfpga.xml
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bug fixed for frame-based configuration memory in top-level full testbench
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2020-06-11 19:31:11 -06:00 |
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k4_N4_40nm_standalone_openfpga.xml
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add new architecture for standalone memory organization
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2020-06-11 19:31:12 -06:00 |
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k6_N10_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_N10_intermediate_buffer_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_chain_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_column_chain_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_register_chain_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_behavioral_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_local_encoder_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_spyio_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_stdcell_mux_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
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k6_frac_N10_tree_mux_40nm_openfpga.xml
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change to a higher simulation clock speed to accelerate CI verification.
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2020-06-11 19:31:03 -06:00 |
