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OpenFPGA/openfpga_flow/tasks
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tangxifan 79b260f5e1 [arch] update missing arch 2022-09-21 16:52:32 -07:00
..
basic_tests [script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment 2022-09-21 10:54:16 -07:00
benchmark_sweep [test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks 2022-09-20 12:08:24 -07:00
compilation_verification/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_bitstream [test] update arch bitstream and force a pin placement for the test case where external bistream is fixed 2022-09-20 14:14:18 -07:00
fpga_sdc/sdc_time_unit [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
fpga_spice/generate_spice/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fpga_verilog [Test] Fix bugs on the remaining implicit verilog test cases 2022-02-15 16:49:15 -08:00
quicklogic_tests [test] now use a fixed routing channel width for quicklogic tests 2022-09-20 12:25:40 -07:00
template_tasks [arch] update missing arch 2022-09-21 16:52:32 -07:00
.gitignore Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
README.md [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00

README.md

Regression tests for OpenFPGA

The regression tests are grouped in category of OpenFPGA tools as well as integrated flows. The principle is that each OpenFPGA tool should have a set of regression tests.

  • compilation_verfication: a quicktest after compilation

  • Basic regression tests should focus on fundamental flow integration, such as

    • Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run

  • FPGA-Verilog regression tests should focus on testing fabric correctness, such as

    • VPR + OpenFPGA integration for a BLIF-to-Verification flow-run

  • FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites

  • FPGA-SDC regression test should focus on SDC file generation and necessary syntax check

  • FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.

  • Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants

  • Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites

Please keep this README up-to-date on the OpenFPGA tools