tangxifan 37c5056d6a [test] now use a fixed routing channel width for quicklogic tests		2022-09-20 12:25:40 -07:00
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counter_5clock_test/config	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
flow_test/config	[test] now use a fixed routing channel width for quicklogic tests	2022-09-20 12:25:40 -07:00
lut_adder_test/config	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
sdc_controller_test/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00