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OpenFPGA/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config
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Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00
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bitstream_annotation.xml [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
task.conf Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00