tangxifan b532bca9d2 [script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment		2022-09-21 10:54:16 -07:00
..
bus_group	[Test] Add missing file	2022-02-20 10:59:44 -08:00
constrain_pin_location/config	[test] fixed a few bugs	2022-07-28 12:06:16 -07:00
custom_fabric_netlist_location/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
explicit_multi_verilog_files/config	[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks	2022-09-20 12:08:24 -07:00
fabric_key	[Test] Bug fix in test cases	2021-10-11 10:28:09 -07:00
fix_pins/config	[Script] Fixed a bug in wrong paths	2022-04-13 16:04:33 +08:00
fixed_device_support/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
fixed_simulation_settings	[test] add a new test case to validate that .act file is not required when power analysis flow is off	2022-08-01 18:44:47 -07:00
full_testbench	[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp	2022-01-25 16:41:36 -08:00
generate_fabric	[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification	2021-04-11 17:26:27 -06:00
generate_testbench/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
global_tile_ports	[Test] Add a test case to validate separated clock pins in global port	2022-03-20 11:02:07 +08:00
k4_series	[test] add test cases to validate the various layouts where I/Os are in the center of the grid	2022-09-16 10:29:19 -07:00
no_time_stamp	[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment	2022-09-21 10:54:16 -07:00
preconfig_testbench	[Test] Update test case by using GPIO with config_done signals	2022-02-24 09:49:34 -08:00
tile_organization	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
verific_test/config	Added 'basic_tests/verific_test' test-case.	2021-11-01 18:20:57 +05:00
write_gsb	[test] add more test cases to validate gsb options	2022-08-29 22:03:06 -07:00
yosys_only/config	Test case for yosys-only flow added	2022-01-14 15:37:47 +05:00