| .. |
|
adder.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
aib.v
|
try to add aib test case. bug found
|
2020-04-12 14:54:45 -06:00 |
|
dff.v
|
[Architecture] Bug fix for dff that are used in data path
|
2020-09-24 17:53:30 -06:00 |
|
dpram.v
|
Adding heterogeneous synthesis requirements
|
2019-12-03 16:09:26 -07:00 |
|
dpram1k.v
|
[Architecture] Add verilog HDL for dual-port BRAM 1k
|
2020-09-22 12:23:28 -06:00 |
|
dpram16k.v
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
dpram_tb.v
|
Adding DPRAM behavioural Verilog netlist and its TB
|
2019-12-03 13:58:20 -07:00 |
|
ff_tb.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
frac_mem_32k.v
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |
|
io.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
latch.v
|
[Architecture] Merge latch Verilog HDL to a unique file
|
2020-09-24 11:02:01 -06:00 |
|
lb_tb.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
lut6.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
mult_32x32.v
|
[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
|
2020-09-22 15:15:19 -06:00 |
|
mult_36x36.v
|
add 36-bit fracturable multiplier Verilog
|
2020-08-18 14:06:08 -06:00 |
|
mux2.v
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
mux_tb.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
sram.v
|
[Architecture] Bug fix in the SRAM Verilog
|
2020-09-24 12:26:13 -06:00 |
|
sram_tb.v
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
3ade6d6ff5