tangxifan 0d882f57b1 Merge branch 'master' into yosys+verific_support		2021-10-30 22:49:21 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Flow] Add comments to clarify the limitations	2021-10-30 19:17:11 -07:00
openfpga_arch	Fixed port names for mult_36x36	2021-10-26 19:14:43 +05:00
openfpga_cell_library	[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected	2021-10-30 11:45:01 -07:00
openfpga_shell_scripts	[Test] Bug fix	2021-10-30 15:48:25 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release	2021-10-30 13:20:58 -07:00
scripts	Adding Yosys+Verific support.	2021-10-29 18:34:27 +05:00
tasks	[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade	2021-10-30 18:05:39 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Change arch for Sapone test	2021-10-30 15:23:19 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00