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fabric_verilog_options.cpp
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streamline fabric verilog options
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2020-07-05 11:28:14 -06:00 |
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fabric_verilog_options.h
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streamline fabric verilog options
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2020-07-05 11:28:14 -06:00 |
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verilog_api.cpp
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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verilog_api.h
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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verilog_auxiliary_netlists.cpp
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_auxiliary_netlists.h
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_constants.h
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_decoders.cpp
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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verilog_decoders.h
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_essential_gates.cpp
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bug fix in power gating support of FPGA-Verilog
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2020-07-22 20:21:38 -06:00 |
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verilog_essential_gates.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_formal_random_top_testbench.cpp
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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verilog_formal_random_top_testbench.h
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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verilog_grid.cpp
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split logical tile netlists to keep good Verilog hierarchy
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2020-07-24 12:53:21 -06:00 |
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verilog_grid.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_lut.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_lut.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_memory.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_memory.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_module_writer.cpp
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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verilog_module_writer.h
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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verilog_mux.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_mux.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_port_types.h
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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verilog_preconfig_top_module.cpp
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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verilog_preconfig_top_module.h
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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verilog_routing.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_routing.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_simulation_info_writer.cpp
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_simulation_info_writer.h
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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verilog_submodule.cpp
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_submodule.h
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_submodule_utils.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_submodule_utils.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_testbench_options.cpp
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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verilog_testbench_options.h
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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verilog_testbench_utils.cpp
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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verilog_testbench_utils.h
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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verilog_top_module.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_top_module.h
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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verilog_top_testbench.cpp
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[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
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2020-09-24 16:31:55 -06:00 |
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verilog_top_testbench.h
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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verilog_wire.cpp
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_wire.h
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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verilog_writer_utils.cpp
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optimizing the constant writing in Verilog for single bits
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2020-06-29 12:29:25 -06:00 |
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verilog_writer_utils.h
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deploy compact constant values in Verilog codes
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2020-06-11 19:31:13 -06:00 |
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