Tarachand Pagarani 50c14e8056 fix CI failures		2021-12-17 07:29:02 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Added 'basic_tests/verific_test' test-case.	2021-11-01 18:20:57 +05:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure	2021-11-12 01:46:06 -08:00
openfpga_arch	Fixed port names for mult_36x36	2021-10-26 19:14:43 +05:00
openfpga_cell_library	[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected	2021-10-30 11:45:01 -07:00
openfpga_shell_scripts	[Test] Bug fix	2021-10-30 15:48:25 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	re-enable counter_5clock,sdc_controller, lut_adder tests	2021-11-19 18:06:06 +05:30
scripts	fix CI failures	2021-12-17 07:29:02 -08:00
tasks	revert unnecessary task.conf changes	2021-11-19 19:07:09 +05:30
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Change arch for Sapone test	2021-10-30 15:23:19 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00