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fix CI failures

This commit is contained in:
Tarachand Pagarani 2021-12-17 07:29:02 -08:00
parent 30bf25017e
commit 50c14e8056
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/scripts/run_fpga_flow.py
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@ -498,7 +498,7 @@ def create_yosys_params():
yosys_args, ExtraArgs = yosysargparser.parse_known_args(yosys_args)
if not args.verific:
if yosys_args.family == "qlf_k6n10f":
if yosys_arg == 1 and yosys_args.family == "qlf_k6n10f":
ys_params["READ_VERILOG_FILE"] = " \n".join([
"read_verilog " + shlex.quote(eachfile)
for eachfile in args.benchmark_files])