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OpenFPGA
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fix CI failures

This commit is contained in:
Tarachand Pagarani 2021-12-17 07:18:04 -08:00
parent 71b0b171b4
commit 30bf25017e
1 changed files with 6 additions and 5 deletions
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11
openfpga_flow/scripts/run_fpga_flow.py
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@ -99,8 +99,6 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
# help="Key file for shell")
parser.add_argument('--yosys_tmpl', type=str, default=None,
help="Alternate yosys template, generates top_module.blif")
parser.add_argument('--yosys_args', type=str, default=None,
help="Arguments for yosys")
parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
help="Alternate yosys template, to rewrite verilog netlist")
parser.add_argument('--verific', action="store_true",
@ -485,19 +483,22 @@ def create_yosys_params():
# Yosys script parameter mapping
ys_params = script_env_vars["PATH"]
yosys_arg = 0
for indx in range(0, len(OpenFPGAArgs), 2):
tmpVar = OpenFPGAArgs[indx][2:].upper()
ys_params[tmpVar] = OpenFPGAArgs[indx+1]
if tmpVar == 'YOSYS_ARGS':
yosys_arg = 1
yosys_args = []
if args.yosys_args:
if yosys_arg == 1:
yosys_args = ys_params["YOSYS_ARGS"].split()
yosysargparser = argparse.ArgumentParser(description="Parses yosys arguments")
yosysargparser.add_argument("-family", type=str, help="Family")
yosys_args = yosysargparser.parse_args(yosys_args)
yosys_args, ExtraArgs = yosysargparser.parse_known_args(yosys_args)
if not args.verific:
if args.yosys_args and yosys_args.family == "qlf_k6n10f":
if yosys_args.family == "qlf_k6n10f":
ys_params["READ_VERILOG_FILE"] = " \n".join([
"read_verilog " + shlex.quote(eachfile)
for eachfile in args.benchmark_files])