| .. |
|
k4_N4_tileable_frac_dsp16_40nm_cell_sim.v
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
|
k4_N4_tileable_frac_dsp16_40nm_dsp_map.v
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
|
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
|
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
|
2021-03-23 15:30:41 -06:00 |
|
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
|
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
|
2021-03-23 15:30:41 -06:00 |
|
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
|
[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
|
2021-04-24 13:30:46 -06:00 |
|
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
|
[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
|
2021-04-24 13:30:46 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
|
[HDL] Rename tech lib to be consistent with arch name changes
|
2021-03-20 18:08:03 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
|
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
|
2021-03-23 15:44:53 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v
|
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
|
2021-03-23 15:44:53 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
|
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
|
2021-03-23 15:44:53 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
|
[HDL] Enriched DFF model in yosys technology library
|
2021-04-21 22:49:05 -06:00 |
|
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
|
[HDL] Enriched DFF model in yosys technology library
|
2021-04-21 22:49:05 -06:00 |
|
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
|
[Script] Update yosys script due to arch changes in DPRAM sizes
|
2021-04-28 10:55:59 -06:00 |
|
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
|
[Script] Update yosys script due to arch changes in DPRAM sizes
|
2021-04-28 10:55:59 -06:00 |
|
k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
|
[Script] Update yosys script due to arch changes in DPRAM sizes
|
2021-04-28 10:55:59 -06:00 |
|
openfpga_adders_sim.v
|
[test] fixed the bug in adder mapping
|
2023-06-20 17:09:31 -07:00 |
|
openfpga_arith_map.v
|
[test] fixed the bug in adder mapping
|
2023-06-20 17:09:31 -07:00 |
|
openfpga_brams.txt
|
[Script] Rename yosys script supporting bram and restructure techlib files
|
2021-03-16 16:16:53 -06:00 |
|
openfpga_brams_map.v
|
[Script] Rename yosys script supporting bram and restructure techlib files
|
2021-03-16 16:16:53 -06:00 |
|
openfpga_brams_sim.v
|
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
|
2021-03-17 15:09:12 -06:00 |
|
openfpga_dff_map.v
|
[arch] fixed a few bugs
|
2022-05-09 17:22:48 +08:00 |
|
openfpga_dff_sim.v
|
[arch] fixed a few bugs
|
2022-05-09 17:22:48 +08:00 |
