ganeshgore 17c4e9a1bb Merge branch 'master' into binder		2022-05-10 19:58:17 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[hdl] add a counter design which is triggered by negative edges	2022-05-09 16:41:21 +08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[Script] Support simplified rewriting for Yosys on output verilog	2022-02-18 14:54:39 -08:00
openfpga_arch	[arch] fixed a few bugs	2022-05-09 17:22:48 +08:00
openfpga_cell_library	[arch] add arch that supports negative edge triggered flip-flop	2022-05-09 16:32:01 +08:00
openfpga_shell_scripts	Update regession tasks	2022-05-05 01:46:19 -06:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[arch] fixed a few bugs	2022-05-09 17:22:48 +08:00
regression_test_scripts	[test] deploy new test to ci	2022-05-09 17:23:57 +08:00
scripts	Minor documentation update	2022-05-08 13:03:16 -06:00
tasks	[test] add a test case to validate negative edge-triggered ff	2022-05-09 16:57:42 +08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[arch] syntax	2022-05-09 17:13:57 +08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00