ganeshgore
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17c4e9a1bb
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Merge branch 'master' into binder
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2022-05-10 19:58:17 -06:00 |
tangxifan
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d7e854eae7
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[test] deploy new test to ci
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2022-05-09 17:23:57 +08:00 |
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tangxifan
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7ed1548c6e
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[arch] fixed a few bugs
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2022-05-09 17:22:48 +08:00 |
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tangxifan
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9f56e61342
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[arch] syntax
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2022-05-09 17:13:57 +08:00 |
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tangxifan
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0afe3a6d33
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[HDL] update dff map rules to support negative triggered ffs
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2022-05-09 16:58:18 +08:00 |
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tangxifan
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22c4d72358
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[test] add a test case to validate negative edge-triggered ff
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2022-05-09 16:57:42 +08:00 |
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tangxifan
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9c7868cfab
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[hdl] add a counter design which is triggered by negative edges
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2022-05-09 16:41:21 +08:00 |
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tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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c8ff3fc8dc
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[test] add regression test to validate compilation of openfpga cell library files
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2022-05-09 16:00:51 +08:00 |
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tangxifan
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d4992fd9ad
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[HDL] Add a multi-mode ff which can support posedge and negedge
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2022-05-09 15:52:17 +08:00 |
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Ganesh Gore
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daae02a614
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Minor documentation update
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2022-05-08 13:03:16 -06:00 |
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Ganesh Gore
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522982c9ba
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Adde vtr_benchmarks_template for demo
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2022-05-06 22:40:36 -06:00 |
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Ganesh Gore
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9473523b6b
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Added VTR arch without fracturable lut
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2022-05-06 11:05:16 -06:00 |
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Ganesh Gore
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275cda081e
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[Bugfix] Typo
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2022-05-05 08:40:21 -06:00 |
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Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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Ganesh Gore
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1e243650b9
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Added option to copy example projects
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2022-05-03 14:06:16 -06:00 |
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Ganesh Gore
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21c3dbf611
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Added regression for template project
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2022-05-02 23:23:45 -06:00 |
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Ganesh Gore
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9891e42f7a
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Added template task
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2022-05-02 11:49:16 -06:00 |
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tangxifan
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9bd66d531e
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[Test] Deploy the new test case to basic regression tests
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2022-04-13 16:06:27 +08:00 |
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tangxifan
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efc25aa66e
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[Script] Fixed a bug in wrong paths
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2022-04-13 16:04:33 +08:00 |
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tangxifan
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5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
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576b9c2d8f
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[Script] Disable SDC writer in multiclock examples
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2022-03-20 11:05:29 +08:00 |
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tangxifan
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3e3a65223c
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[Test] Deploy new test case to basic regression tests
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2022-03-20 11:04:07 +08:00 |
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tangxifan
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f8845f7d3a
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[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
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tangxifan
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c8da85cc24
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[Doc] Update naming convention for OpenFPGA architecture files
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2022-03-20 10:51:55 +08:00 |
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tangxifan
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a1e2d9c864
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[Arch] Add a new example openfpga arch where clock ports are independent
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2022-03-20 10:50:31 +08:00 |
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tangxifan
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9f7a182433
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[Arch] Typo
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2022-02-24 09:51:26 -08:00 |
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tangxifan
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fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
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fcaff28e24
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[HDL] Add a new IO cell with config_done support
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2022-02-24 09:46:55 -08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
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e443a4567d
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[Arch] Typo
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2022-02-23 22:09:26 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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cf31879b20
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[Test] Deploy new test to basic regression tests
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2022-02-23 16:03:56 -08:00 |
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tangxifan
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245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
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785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
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68644ea0f6
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[Test] Add the new test to basic regression tests
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2022-02-18 15:44:07 -08:00 |
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tangxifan
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f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
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fe9e0ff977
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[Test] Add the new test to basic regression tests
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2022-02-18 15:38:53 -08:00 |
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tangxifan
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c897a64ad5
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[Script] Add a new example script to test full testbenches using bus group features
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2022-02-18 15:37:42 -08:00 |
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tangxifan
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223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
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85c893c94c
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[Test] Add new test to basic regression tests
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2022-02-18 15:30:08 -08:00 |
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tangxifan
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5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
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b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
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36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
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8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
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a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |