tangxifan
|
c8da85cc24
|
[Doc] Update naming convention for OpenFPGA architecture files
|
2022-03-20 10:51:55 +08:00 |
|
tangxifan
|
a1e2d9c864
|
[Arch] Add a new example openfpga arch where clock ports are independent
|
2022-03-20 10:50:31 +08:00 |
|
tangxifan
|
9f7a182433
|
[Arch] Typo
|
2022-02-24 09:51:26 -08:00 |
|
tangxifan
|
fdaf97e60d
|
[Test] Update test case by using GPIO with config_done signals
|
2022-02-24 09:49:34 -08:00 |
|
tangxifan
|
e443a4567d
|
[Arch] Typo
|
2022-02-23 22:09:26 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
62b4a0b7ff
|
[Flow] Add openfpga arch for DSP with registers
|
2022-01-02 19:59:33 -08:00 |
|
tangxifan
|
7598455497
|
[Doc] Update naming convention for architecture files
|
2022-01-02 19:51:09 -08:00 |
|
tangxifan
|
b8d5920529
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-28 15:45:58 -07:00 |
Aram Kostanyan
|
2eef21a1af
|
Fixed port names for mult_36x36
|
2021-10-26 19:14:43 +05:00 |
|
tangxifan
|
82e77b42c5
|
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
|
2021-10-09 20:43:55 -07:00 |
|
tangxifan
|
d2859ca1c8
|
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
|
2021-10-05 10:56:20 -07:00 |
|
tangxifan
|
fbef22b494
|
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
|
2021-10-04 16:39:53 -07:00 |
|
tangxifan
|
86e7c963f8
|
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
|
2021-10-02 22:19:20 -07:00 |
|
tangxifan
|
7ba5d27ea7
|
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
|
2021-10-01 17:02:35 -07:00 |
|
tangxifan
|
fa57117f50
|
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
|
2021-10-01 10:19:51 -07:00 |
|
tangxifan
|
41cc375746
|
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
|
2021-09-29 16:34:40 -07:00 |
|
tangxifan
|
4968f0d11f
|
Merge branch 'master' into qlbank_sr
|
2021-09-28 14:20:30 -07:00 |
|
tangxifan
|
80232fc459
|
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
|
2021-09-28 12:36:36 -07:00 |
|
tangxifan
|
4c04c0fbd7
|
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
|
2021-09-28 12:35:42 -07:00 |
|
tangxifan
|
4aed045cdd
|
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
|
2021-09-28 11:34:20 -07:00 |
|
tangxifan
|
a98df811ed
|
[Arch] Bug fix: wrong circuit model name was used for CCFF
|
2021-09-22 15:50:47 -07:00 |
|
tangxifan
|
53da5d49fe
|
[Arch] Correct XML syntax errors
|
2021-09-22 15:48:14 -07:00 |
|
tangxifan
|
3cfd5c3531
|
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
|
2021-09-22 15:04:59 -07:00 |
|
tangxifan
|
212c5bd642
|
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
|
2021-09-22 15:04:19 -07:00 |
|
tangxifan
|
d0fe12fadd
|
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
|
2021-09-22 10:03:39 -07:00 |
|
tangxifan
|
0450d57d82
|
[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
|
2021-09-20 16:05:01 -07:00 |
|
tangxifan
|
cd2978a434
|
[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
|
2021-09-20 11:13:02 -07:00 |
|
tangxifan
|
6be3c64f1c
|
[Arch] Add an example architecture using the physical design friendly memory bank organization
|
2021-09-09 09:22:27 -07:00 |
|
tangxifan
|
dcb89cb16b
|
[Arch] Patch architecture due to missing mode bit definition
|
2021-07-02 11:41:29 -06:00 |
|
tangxifan
|
fd85f956c9
|
[Arch] Update k4n4 arch with true multi-mode flip-flop
|
2021-07-02 11:08:39 -06:00 |
|
tangxifan
|
f77b81fe5b
|
[Arch] recover the mem16k arch as it is used in other test cases
|
2021-04-28 15:05:30 -06:00 |
|
tangxifan
|
117cea295d
|
[Arch] Patch architecture to be compatible with pin names of DPRAM cell
|
2021-04-28 11:28:23 -06:00 |
|
tangxifan
|
ec4b60f3cc
|
[Arch] Add example arch using 1-kbit DPRAM
|
2021-04-28 10:47:17 -06:00 |
|
tangxifan
|
be98775ae5
|
[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
|
2021-04-28 10:45:10 -06:00 |
|
tangxifan
|
834657f2da
|
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
|
2021-04-27 23:41:14 -06:00 |
|
tangxifan
|
0f8aaae2bc
|
[Arch] Patch architecture using 16kbit dual port RAM
|
2021-04-27 19:54:34 -06:00 |
|
tangxifan
|
a3a98fa21d
|
[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
|
2021-04-24 14:56:10 -06:00 |
|
tangxifan
|
4f454abfde
|
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
|
2021-04-24 14:01:42 -06:00 |
|
tangxifan
|
ddcdb35b28
|
[Arch] Bug fix in single-mode 8-bit DSP architectures
|
2021-04-24 13:30:03 -06:00 |
|
tangxifan
|
ce6018e123
|
[Arch] Enriched DFF model to support active-low/high FFs
|
2021-04-21 22:48:31 -06:00 |
|
tangxifan
|
9d9840d9b7
|
[Arch] Add architecture using multi-mode DFFs
|
2021-04-21 19:49:48 -06:00 |
|
tangxifan
|
16e02ef485
|
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
|
2021-04-16 20:47:39 -06:00 |
|
tangxifan
|
4239bb4e68
|
[Arch] Patch architecture files using multi-mode DFFs
|
2021-04-16 19:59:55 -06:00 |
|
tangxifan
|
f2f7f010ea
|
[Arch] Add new architectures using DFF with reset in VPR
|
2021-04-16 19:26:18 -06:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |
|
tangxifan
|
44d97ead86
|
Merge branch 'master' into hetergeneous_arch
|
2021-03-23 17:05:03 -06:00 |
|
tangxifan
|
fdec72b5bc
|
[Arch] Add an example architecture with 8-bit single-mode multiplier
|
2021-03-23 15:35:06 -06:00 |
|
tangxifan
|
911979a731
|
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
|
2021-03-20 18:04:59 -06:00 |
|
tangxifan
|
910f8471dd
|
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
|
2021-03-17 15:10:05 -06:00 |