tangxifan
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907308ee0f
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[Doc] Update bitstream distribution file format
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2022-03-29 20:09:24 +08:00 |
taoli4rs
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781250f0bb
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Fix a small typo to trigger the CI flow.
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2022-03-22 16:36:45 -07:00 |
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tangxifan
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6ff69d26b9
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[Doc] An example to the documentation about the new feature in tile_annotation
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2022-03-20 13:12:13 +08:00 |
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tangxifan
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123bb70cb3
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[Doc] More explanantion on the use of config_enable attribute for circuit ports
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2022-02-23 15:53:58 -08:00 |
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tangxifan
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b78e58d9bf
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[Doc] Update doc about big endian syntax in bus group file format
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2022-02-18 23:07:18 -08:00 |
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tangxifan
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8116141210
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[Doc] Update documentation on the bus group feature
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2022-02-18 15:46:25 -08:00 |
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tangxifan
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37d8617a5c
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[Doc] Update due to new options
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2022-02-17 19:45:37 -08:00 |
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tangxifan
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4a78bcf5d3
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[Doc] update file format about bus group
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2022-02-17 15:15:05 -08:00 |
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tangxifan
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f5e0d685cf
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[Doc] Adjust figure width
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2022-02-17 14:29:09 -08:00 |
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tangxifan
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796428d848
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[Doc] Add documentation about bus group file format
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2022-02-17 14:22:21 -08:00 |
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tangxifan
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2b5fded2a9
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[Doc] Update documentation on the new option
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2022-02-01 13:25:58 -08:00 |
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tangxifan
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b7b0a2a5d8
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[Doc] Update doc about the new option
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2022-02-01 12:19:26 -08:00 |
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tangxifan
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63f44adf15
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[FPGA-Verilog] Now have a new option ``--use_relative_path``
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2022-01-31 12:48:05 -08:00 |
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tangxifan
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a9a56686e2
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[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
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2022-01-26 11:10:29 -08:00 |
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tangxifan
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25143d07f1
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[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
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2022-01-25 13:37:54 -08:00 |
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tangxifan
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a4659020f2
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Merge branch 'master' into time_stamp
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2022-01-25 12:11:35 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
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Aram Kostanyan
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2b008177e7
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Updated documentation.
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2022-01-17 14:58:20 +05:00 |
Awais Abbas
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54d4f30592
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OpenFPGA Documentation updated for yosys only support
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2022-01-14 16:14:48 +05:00 |
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tangxifan
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80c6d5887d
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Merge branch 'ql_mem_bank_opensource' of https://github.com/RapidSilicon/OpenFPGA_RS into ql_mem_bank
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2021-12-29 10:57:46 -08:00 |
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tangxifan
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b2ba0d0c42
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[Doc] Add version naming convention to developer guidelines
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2021-12-22 15:12:14 -08:00 |
nadeemyaseen-rs
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236910cde4
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-12-09 00:00:21 +05:00 |
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tangxifan
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1e5afb985c
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Update contact.rst
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2021-11-30 20:25:15 -08:00 |
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nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
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tangxifan
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b8d5920529
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-28 15:45:58 -07:00 |
Ganesh Gore
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130805d50c
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Updated CI documentation
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2021-10-21 15:17:30 -06:00 |
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nadeemyaseen-rs
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e0cfd46ec7
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-10-14 19:25:31 +05:00 |
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tangxifan
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57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
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03bcf6dee5
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[Doc] Update documenation for the new option ``--keep_dont_care_bits``
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2021-10-05 19:23:42 -07:00 |
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tangxifan
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ff339312f6
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[Doc] Update documentation about the limitations of multi-region configuration protocols
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2021-10-05 11:55:10 -07:00 |
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tangxifan
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9a7e0f761a
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[Doc] Add fabric bitstream file format for QL memory bank
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2021-10-04 12:29:49 -07:00 |
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tangxifan
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a01fa7c282
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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tangxifan
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b0a97a7052
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[Doc] Update doc about WLR usage for QL memory bank
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2021-09-27 10:24:04 -07:00 |
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tangxifan
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f9bceff33a
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[Doc] Update documentation for the flatten BL/WL protocols
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2021-09-25 20:44:45 -07:00 |
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tangxifan
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10774dc15c
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[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
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3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
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73d21c9730
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[Doc] Update doc about how to use the QuickLogic memory bank
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2021-09-10 15:30:37 -07:00 |
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tangxifan
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801b91f776
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Merge branch 'master' into tutorials
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2021-08-31 17:17:40 -07:00 |
ANDREW HARRIS POND
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1c09b8c3e0
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fixed python instruction
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2021-08-17 10:18:51 -06:00 |
bbleaptrot
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814d290463
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Merge branch 'master' into tutorials
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2021-08-05 10:24:34 -06:00 |
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bbleaptrot
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c867c7e628
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Update index to include FAQ page
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2021-07-28 10:14:31 -06:00 |
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bbleaptrot
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2bb76e4a82
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Update to include suggested changes
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2021-07-28 10:13:25 -06:00 |
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bbleaptrot
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17d3fb5d5e
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Add FAQ to source folder to go along in appendix
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2021-07-28 10:10:17 -06:00 |