tangxifan
|
03a64e2ad8
|
complete the mutators for ports
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2019-08-07 20:54:27 -06:00 |
|
tangxifan
|
9f8c7a3fc7
|
adding port mutators
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2019-08-07 17:47:39 -06:00 |
|
tangxifan
|
ed4642a23f
|
adding basic mutators
|
2019-08-07 17:12:05 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
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tangxifan
|
55bfaf271d
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Merge branch 'dev' into std_map_support
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2019-08-06 14:38:19 -06:00 |
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tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
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2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b207050b03
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minor fix in documentation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
fc93a4941a
|
update documentation
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
7603850d72
|
complete documentation for new features
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
33f3a991b5
|
init effort to start developing mux local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
7748340314
|
hot fix on tutorial
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
2291c52fab
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-30 16:54:55 -06:00 |
|
tangxifan
|
8a046394f8
|
add documentation for multi-mode configurable block support
|
2019-07-30 16:47:41 -06:00 |
AurelienUoU
|
40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-29 11:45:23 -06:00 |
|
tangxifan
|
716c3c63c3
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-27 15:06:06 -06:00 |
|
AurelienUoU
|
7d469d8b4f
|
Docker try 2
|
2019-07-22 13:06:46 -06:00 |
|
AurelienUoU
|
52b754f9c1
|
Update
|
2019-07-22 10:14:03 -06:00 |
|
AurelienUoU
|
0854161a63
|
Docker update
|
2019-07-22 09:42:31 -06:00 |
|
AurelienUoU
|
64a67dceaf
|
Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
|
2019-07-18 16:34:47 -06:00 |
|
AurelienUoU
|
f4e999ef6d
|
Correct error in demo, set a new generated ff_${benchmark}.v file rather than overwrite
|
2019-07-18 16:33:23 -06:00 |
|
tangxifan
|
73d6d5264a
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-18 13:40:19 -06:00 |
|
tangxifan
|
434c0d9683
|
hot fix on tutorial
|
2019-07-18 13:39:47 -06:00 |
|
Xifan Tang
|
173440ffc3
|
retry
|
2019-07-17 18:46:54 -04:00 |
|
Xifan Tang
|
8226f42d3d
|
use hfill to place image inline
|
2019-07-17 18:46:14 -04:00 |
|
Xifan Tang
|
a80199057d
|
logo placement
|
2019-07-17 18:43:17 -04:00 |
|
Xifan Tang
|
37abd8af40
|
try to place inline logo
|
2019-07-17 18:40:26 -04:00 |
|
Xifan Tang
|
f3ed949c4b
|
retry placing images
|
2019-07-17 18:36:49 -04:00 |
|
Xifan Tang
|
b104de0263
|
resize logo again
|
2019-07-17 17:56:06 -04:00 |
|
Xifan Tang
|
b850610cea
|
resize logo to fit
|
2019-07-17 17:55:10 -04:00 |
|
Xifan Tang
|
17308621bd
|
resize logo on README
|
2019-07-17 17:53:36 -04:00 |
|
Xifan Tang
|
af335dff66
|
Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
|
2019-07-17 17:51:45 -04:00 |
|
Xifan Tang
|
afd78604c9
|
Merge branch 'dev' into documentation: resolved conflicts and add logo files
|
2019-07-17 17:50:11 -04:00 |
|
Xifan Tang
|
6af0d277a2
|
hot fix on fpga logo
|
2019-07-17 17:48:01 -04:00 |
|
Xifan Tang
|
5bec11bd6e
|
try to add logo
|
2019-07-17 17:46:25 -04:00 |
|
Xifan Tang
|
e7b40f06b0
|
Add documentation for fracturable LUTs
|
2019-07-17 15:21:07 -04:00 |
|
tangxifan
|
8a92a3b589
|
Merge pull request #19 from LNIS-Projects/egiacomin-patch-5
Update how2use.md
|
2019-07-17 14:34:23 -04:00 |
egiacomin
|
922e40131f
|
Update how2use.md
|
2019-07-17 12:33:15 -06:00 |
|
tangxifan
|
a16dae6d8c
|
Merge pull request #18 from LNIS-Projects/egiacomin-patch-4
Egiacomin patch 4
|
2019-07-17 14:33:12 -04:00 |
|
AurelienUoU
|
5947818761
|
Typo correction
|
2019-07-17 12:23:06 -06:00 |
|
egiacomin
|
1da04b9c3a
|
Update tutorial_index.md
|
2019-07-17 12:19:57 -06:00 |