tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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85921dcc05
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add fabric bitstream builder for frame-based configuration protocol
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8c14cced84
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start improve fabric bitstream database to support frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
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3807a940f4
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fixed critical bugs in bitstream generation and now we pass microbenchmarks
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2020-02-28 16:45:50 -07:00 |
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tangxifan
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410dcf6ab6
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debugged LUT bitstream
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2020-02-26 11:42:18 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |
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tangxifan
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075264e3e3
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debugging LUT bitstream generation
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2020-02-25 23:29:16 -07:00 |
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tangxifan
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2c44c70557
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bring pb interconnection bitstream generation online
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2020-02-25 00:28:06 -07:00 |
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tangxifan
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04c69d30c2
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start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
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2020-02-24 19:38:02 -07:00 |
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tangxifan
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712eeb1340
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bring bitstream generator for routing modules online
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2020-02-23 22:09:46 -07:00 |
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tangxifan
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86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |
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tangxifan
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8723007f68
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Bring mux bitstream generation online
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2020-02-23 20:53:24 -07:00 |
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tangxifan
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51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |