tangxifan
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e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
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b9dab2baaf
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add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
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tangxifan
|
1fb37f4c71
|
improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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tangxifan
|
0b1c8ac139
|
bug fixed in identifying the physical interconnect for pb_graph nodes
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2020-04-07 19:46:42 -06:00 |
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tangxifan
|
62276f9e28
|
minor code format
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2020-04-07 18:43:11 -06:00 |
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tangxifan
|
cbcd1d20d4
|
fixed memory leakage in pb_pin fixup
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2020-04-07 16:24:04 -06:00 |
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tangxifan
|
5a04da2082
|
fix memory leakage in openfpga title
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2020-04-07 16:14:41 -06:00 |
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tangxifan
|
26d1261c1f
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add test cases using shift registers
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2020-04-07 15:09:10 -06:00 |
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tangxifan
|
92a3a444f9
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update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
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tangxifan
|
3369d724e9
|
bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
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tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
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tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
|
5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
|
bc47b3ca94
|
update verilog module writer to the global spy ports
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2020-04-05 16:04:13 -06:00 |
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tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
|
836f722f20
|
start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
|
63306ce3a0
|
add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
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tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
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tangxifan
|
329b0a9cf1
|
add options to enable SDC constraints on zero-delay paths
|
2020-03-25 15:55:30 -06:00 |
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tangxifan
|
4a0128f240
|
minor fix on the SDC format
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2020-03-25 14:46:31 -06:00 |
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tangxifan
|
c2e5d6b8e2
|
add options to dsiable SDC for non-clock global ports
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2020-03-25 14:38:13 -06:00 |
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tangxifan
|
787dc8ce83
|
added ASCII OpenFPGA logo in shell interface
|
2020-03-25 11:16:04 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
9e4e12aae9
|
fixed echo message in the compression rate of gsb uniquifying
|
2020-03-22 16:13:04 -06:00 |
|
tangxifan
|
ff474d87de
|
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
|
2020-03-22 16:11:00 -06:00 |
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tangxifan
|
fdf6a6bd3e
|
use chan_node_in_edges from rr_gsb in XML writer
|
2020-03-22 15:48:11 -06:00 |
|
tangxifan
|
3958ac2494
|
fix bugs in flow manager on default compress routing problems
|
2020-03-22 15:26:15 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
|
tangxifan
|
7b9384f3b2
|
add write_gsb command to shell interface
|
2020-03-21 19:40:26 -06:00 |
|
tangxifan
|
637be076dc
|
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
|
2020-03-21 18:49:20 -06:00 |
|
tangxifan
|
9a518e8bb6
|
bug fixed for tileable rr_graph builder for more 4x4 fabrics
|
2020-03-21 18:07:00 -06:00 |
|
tangxifan
|
c0e8d98c6f
|
bug fixed in tile direct builder
|
2020-03-21 12:43:56 -06:00 |
|
tangxifan
|
8f35f191eb
|
use the formalized function in FPGA-SDC to identify direct connection
|
2020-03-21 11:42:00 -06:00 |
|
tangxifan
|
28123b8052
|
remove the direct connected IPIN/OPIN from RR GSB builder
|
2020-03-21 11:38:39 -06:00 |
|
tangxifan
|
682b667a3c
|
minor bug fix for direct connection in FPGA-SDC
|
2020-03-20 21:44:01 -06:00 |
|
tangxifan
|
05ec86430a
|
temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
|
2020-03-20 17:56:03 -06:00 |
|
tangxifan
|
2c0c5a061b
|
spot a bug in assigning rr_switch in tileable routing
|
2020-03-20 16:53:43 -06:00 |
|
tangxifan
|
a46fc9f028
|
add debugging information for tile direct builder
|
2020-03-20 14:59:46 -06:00 |
|
tangxifan
|
808853db0b
|
critical bug fixed for find proper pb_route traceback
|
2020-03-13 12:26:37 -06:00 |
|
tangxifan
|
81e5af464e
|
improve lb_route to avoid routing combinational loops
|
2020-03-12 23:58:56 -06:00 |
|
tangxifan
|
773e6da308
|
Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
|
2020-03-12 22:53:17 -06:00 |
|
tangxifan
|
29450f3472
|
debugging multi-source lb router
|
2020-03-12 20:42:41 -06:00 |
|
tangxifan
|
8921905bec
|
annotate multiple-source and multiple-sink nets from pb to lb router
|
2020-03-12 19:21:13 -06:00 |
|
tangxifan
|
f0b22aaa11
|
Make lb router support multiple sources to be routed
|
2020-03-12 13:44:14 -06:00 |
|
tangxifan
|
c40675ca9d
|
minor code formatting
|
2020-03-12 11:55:25 -06:00 |
|
tangxifan
|
f1e8e78410
|
minor code formatting
|
2020-03-12 11:47:42 -06:00 |
|
tangxifan
|
689c50dff1
|
label the routing status for each sink in lb_router
|
2020-03-12 11:36:31 -06:00 |